Looking to multimode radio demands for 4G wireless infrastructure solutions, Ceva Inc. announced its CEVA-XC323 vector DSP core.
The CEVA-XC323, operating at up to 1Ghz, claims a quadrupling of performance in wireless infrastructure applications compared with incumbent infrastructure VLIW DSPs, a strong suit of Texas Instruments, which is backing off the baseband business.
512-bit SIMD operations
32 MAC operations per cycle
Supports wireless standards such as WCDMA, HSPA, WiMAX, LTE and LTE-A.
Given, the rapid expansion of demands in the wireless infrastructure, system designers are looking for increased flexibility and scalability (see chart below), said Eran Briman, Ceva's vice president of marketing.
"TI's approach was a general-purpose DSP.... not dedicated for specific functions," he said. "The XC is specifically used for wireless communications. The (TI) C64 is used for video and audio processing. When you go to 4G processing servicing 100,000 users at same time, it doesn't work. This really allows you to run everything in software. You'll be able to run 3G, 2G, 4G on the same die...all on the same SoC."
While Ceva positions itself against TI, it's also competing against cores-based solutions such as those from Tensilica, which offers technologies such as the Xtensa LX3 DSP for vector DSP duty.
It's intended to be scalable--designers can use the same DSP for femtocells to macro-bastations because it runs in software. "You take the DSP at 200MHz for a femtocell all the way to a GHz for those basestations," Briman said.
Wireless infrastructure demands
# of users
4 / 8 /16
In building / small area
16 / 32
The CEVA-XC323 includes an integrated Power Scaling Unit (PSU), which provides advanced power management for both dynamic and leakage power.
The core supports multiple voltage domains associated with the main
functional units, such as the DSP logic, the instruction and data
memories, and so forth.
The core also supports multiple operational modes ranging from full
operation, to debug bypass, to memory retention, to complete power
shut-off (PSO). Furthermore, the AXI full duplex buses offer low-power
features, such as ability to shut down when no data traffic is present
The CEVA-XC323 DSP architecture is compiler-driven, implementing an orthogonal instruction set so as to ensure optimal utilization of the processor capabilities from C-level. The processor is supported by CEVA-Toolbox, the company's integrated development environment (IDE)
The CEVA optimizing C-compiler supports the CEVA Vec-C™ language extensions for vector processors, enabling the entire architecture to be programmed in C-level. An integrated simulator provides accurate and efficient verification of the entire system including the memory sub-systems. In addition, CEVA-Toolbox includes libraries, a graphical debugger, and a complete optimization tool chain named CEVA Application Optimizer.
The device is software compatible with the CEVA X DSP family, which includes the:
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