Lattice Semiconductor today announced the immediate availability of the PCI Express Root Complex (RC) Lite solution based on the LatticeECP3 and LatticeECP2M FPGA families for use in simple bridging application to any legacy host bus.
Using a low cost programmable FPGA platform, designers can implement the specific bridge function that matches the interface available on their particular host CPU. Designers will also have the flexibility to implement multiple bridges or different configurations of bridges in a single FPGA, reducing the number of components on the board.
Lattice's PCI Express RC Lite solution is supported by Lattice’s IPexpress FPGA design tool module. Included as a standard feature in the Lattice Diamond design environment, the IPexpress module significantly reduces design time by allowing IP parameterization and timing analysis on the designer’s desktop. This allows users to customize Lattice's extensive library of IP functions for their unique applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.
The PCI Express RC Lite IP core provides a x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in the PCI express protocol stack. The PCI Express 1.1 x1 RC Lite IP core requires approximately 4500 FPGA look-up tables (LUTs) in 16-bit mode. The PCI Express 1.1 x4 RC Lite IP core requires approximately 10,500 FPGA LUTs in 64-bit mode.
Pricing and Availability
The PCI express root complex IP core is available now, with a low list price of $1,500 for the x1 IP core and $3,000 for the x4 IP core and can be ordered through Lattice sales (firstname.lastname@example.org) (Click Here for more information about the IP core).
About the LatticeECP3 FPGA Family The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/Os. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireline and wireless infrastructure applications.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.