The BEE4-W is BEEcube's latest generation FPGA (Field Programmable Gate Array) Berkeley Emulation Engine (BEE) platform, specifically designed to address rapid system-level prototyping of wireless and digital communications designs. It is stackable, full-speed, and multi-FPGA based. With four (4) integrated ADC and DAC solutions, the Xilinx Virtex-6 FPGA based BEE4-W enables a wide range of high-performance, real-time implementations in multiple military and defense applications.
BEE4-W allows for flexible algorithm and feature set definitions and is a true real-time development and deployment platform for radar applications, signal intelligence, MIMO communications, software defined radio (SDR), and wireless (Digital Based RF) algorithm applications. The latest signal processing algorithms can be rapidly prototyped and deployed, running at clock rates of hundreds of MHz, which directly interface to multi-GHz and integrated A/D and D/A converters.
The FMC DAC/ADC Module comprises four sets of a single-width FMC mezzanine card, providing both a 12-bit, 2.3-GSps multi-Nyquist digital-to-analog converter and a 12-bit, 1-GSps analog-to digital converter. BEE4-W DAC/ADCs are based on Maxim MAX19692 and Texas Instruments ADS5400 components.
Each BEE4-W system or module consists of four Xilinx Virtex-6 FPGAs based on a unique HPC (High Performance Computing) Honeycomb architecture. BEE4 modules can be stacked or clustered to increase capacity without losing speed. Using Sting I/O and depending on the design, users can run prototype logic up to 500 MHz and digital interface communication at 640 Gbps per BEE4-W module, including optical interfaces and multiple Digital to Analog and Analog to Digital components. BEE4-W supports the latest FMC and QSPF+ interface standards.
BEE4-W modules support of a variety of high-end Virtex-6 FPGAs, including LXT 240/365/550 and SXT 315/475, allowing BEE4-W to support 20 MGate designs per module, or 400 MGates per rack.
A single BEE4-W has a maximum capacity of 20M ASIC gates, and the quad FPGA design is interconnected with a ring bus and integrated DDR3-800/1066 memory. Each BEE4 FPGA follows a symmetrical design, including identical memory and independent I/Os. Multiple high-speed data interfaces include: 160 Gbps QSFP+, x8 Gen2 PCI Express, Quad 1000BASE-T Ethernet, and Quad FMC expansion slots. The system has a capability of buffering 128GB of data in DDR3 memory.
BEE4-W is bundled with a unique clusterable Honeycomb symmetrical architecture; the industry's highest available inter-FPGA and BEE4 module to module communication via Sting I/O; programmable application access to your FPGA code, via BEEcube's distributed Nectar OS; and an algorithm development and IP library environment with BEEcube Platform Studio (BPS).
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