I was having an interesting chat with the folks from eASIC the other day. As you may recall, they have a rather interesting Structured ASIC fabric, which can be configured using only a single via layer.
The ability to configure the device using only a single via layer has a number of implications, not the least that the turnaround time to get prototype (and then production) silicon back from the foundry is really fast. Equally important is that fact that the folks at eASIC have pre-characterized and analyzed all of the track segments and created the base devices in such a way as to minimize (largely eliminate) any signal integrity problems.
Also of interest is the fact that they have something called a “Green Power Via” … the idea here is that if your design occupies only say 70% of the device, then these vias can be used to completely turn off the remaining 30% such that it consumes no power.
All of this is extremely important when it comes to the challenges seen by the folks who create wireless base stations. These challenges include an ongoing exponential growth in data traffic, the need to accommodate multiple wireless standards, lots of competition, and the need for extreme power and thermal efficiency.
The folks at eASIC say that ASICs and ASSPs are really expensive and take a lot of time and resources to develop, while FPGAs are expensive and consume a lot of power. On this basis, the eASIC Structured ASIC fabric is really very attractive… but creating a wireless base station from the ground up is a major feat… unless you have access to the right IP…
Consider, for example, the Common Public Radio Interface (CPRI), which is the most widely deployed interface between baseband and radio sections of a wireless base station. CPRI has traditionally been implemented using expensive and high power consumption FPGAs.
Now, the folks at eASIC have teamed up with the guys and gals at Radiocomp (providers of modular RF systems and components for mobile and wireless infrastructure networks) to offer an alternative solution. In fact they have just announced the mmediate availability of a low power Common Public Radio Interface (CPRI) v4.1 solution for Radio Equipment Controller (REC) equipment. Using the low power transceivers on eASIC Nextreme-2T NEW ASICs, and the industry proven CPRI v4.1 REC IP core from Radiocomp, the solution consumes only 190 mW per channel at 6.144 Gbps.
N2XT CPRI 6.144 Gbps Eye Diagram
The combination of CPRI v4.1 IP and eASIC Nextreme-2T NEW ASICs enables base-station baseband module suppliers to accelerate cost reductions of FPGA-based designs and at the same time decrease power consumption by up to 80%.
The availability of the eASIC CPRI REC solution allows FPGA designers to engage in cost and power reduction efforts much sooner, and at a fraction of the development cost for cell-based ASICs.
The Radiocomp CPRI v4.1 core has already been verified in both FPGAs and eASIC devices and features:
- Built-in support for CPRI v4.1 REC and backwards compatible mapping methods
- Programmable Line rates up to 6.144 Gbps.
- Up to 32 antenna carriers per IP core
- Integrated HDLC and 10/100 Ethernet MAC controllers or external MII interface
- Portable HDL code for easy migration from FPGAs to eASIC