Today Synopsys, Inc. announced the availability of the DesignWare® DDR PHY compiler, supporting DDR2, DDR3, LPDDR and LPDDR2 SDRAMs. According to Synopsys, the DesignWare DDR PHY compiler provides a web-based GUI to assemble a customized, high-performance DDR PHY for a system-on-chip (SoC) design. The new compiler evaluates more than 60 variables and allows the evaluation of unlimited 'what-if' scenarios. The output of the PHY compiler is a customized hard DDR PHY that is optimized for the target application.
Designers have control over multiple variables including supported DRAM types (such as DDR3, DDR2, Mobile DDR and/or LPDDR2), foundry and process node, memory channel width, power-to-signal ratios, core power requirements and other physical placement variables. The DesignWare DDR PHY compiler produces an instantly viewable image of the DDR PHY layout, a list of the pins, area, a power consumption report, placement scripts and an RTL model of the PHY.
Synopsys will be demonstrating the DesignWare DDR PHY compiler at the upcoming DesignCon 2011 Conference (booth number 606) on February 2-3 at the Santa Clara Convention Center in Santa Clara, California.
The DesignWare DDR PHY compiler is available to licensed customers of select DesignWare DDR PHY IP today. For access to the DesignWare DDR PHY compiler as part of the Synopsys "Try the PHY" program, visit: https://www.synopsys.com/dw/ddrphy.php
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