PARIS – Blue Pearl Software Inc. (Santa Clara, Calif.) claimed it is proposing a transformative approach with the introduction of its Blue Pearl Suite for automating design analysis, CDC (clock domain crossing) checking, SDC (Synopsys Design Constraints) creation, visualization and validation.
The proprietary technologies used by Blue Pearl Software include RTL analysis, high-level symbolic simulation and state space exploration. These technologies have been developed over many years by the founders of Blue Pearl and are the foundation for existing and future products to address verification needs of large designs at RTL or the functional level.
In an interview with EE Times, Blue Pearl's CEO Ellis Smith indicated that the company has integrated these technologies into a single executable program, the Blue Pearl Suite, for fast design analysis, CDC checking and timing constraint generation, management and validation.
He explained: "We have taken these technologies and, in one run of the software, anybody can do design analysis, clock domain checking and also automatically identify very complex false and multi-cycle paths and then generate design constraints in the Synopsys Design constraints format. And, what makes our software unique is that we use a user environment that is native to Windows and Linux and enables somebody to do these very complex tasks very easily and quickly."
Blue Pearl had a software suite before. Smith noted that the company enhanced it by adding the Visual Verification environment and a new user experience where the functions of design analysis and CDC checking become easy to use by designers and intuitive.
"I think previously only very experienced designers could use a tool to do cross domain checking," Smith stated. "What we really want to do is give designers, whether they are FPGA or ASIC designers, the ability to have as early as possible the highest level of confidence in their design. We feel that this very intuitive, native interface really helps people. It transforms their existing design flow into something that is really easy to use."
Smith highlighted the tool's ability to make clock domain checking accessible to any level of designers, and people can check their work automatically by clicking on the checks and looking at the schematics.
Indeed, he explained that the main reason why people are having clock domain issues is that now designers have many clocks where different portions of the design are gated. They are turning off areas of the design or areas of the chip to save power so the whole reason the design has multiple clocks now is a power issue. Because of that, instead of designs that have one or two clocks, they can have ten, fifteen, fifty clocks and as you have data passing from one clock domain to the next, you have to verify that this data arriving at the next domain is synchronized. That's the whole issue behind CDC, and why it is becoming a hot issue, outlined Smith.
The other issue, he continued, is that because of what is happening with the complexity of FPGAs, CDC is becoming a hot issue with FPGA designers. "We made this new useful design flow for people who are not used to using Windows and also do not have the level of experience of ASIC designers. It is meant at ASIC and FPGA designers. I believe right now it is the only CDC tool available on Windows."
Also of interest, Blue Pearl Software Suite automatically generates timing constraints in the Synopsys Design Constraints format. The technology, Smith notified, enables to identify very complex false and multi-cycle paths. A false path is a path in the design that is not activable in a certain clock cycle. A multi-cycle path is a path in a design that is activable in several clock cycles.
SDC path view
Click on image to enlarge
He described the process: "We automatically generate design constraints in the Synopsys Design Constraints format and then, in our tool, you can click on these constraints and, in the next window, you will see the starting point of that path. In a third window, called visual verification, you can view that path in a schematic, so the designers can look and see that this is a false path."
So, Smith concluded, it gives designers an instant way to validate that what has been done automatically is right and accurate.
Asked if the Blue Pearl Suite has been tested by a select set of customers, Smith said the company has users for the underlying technology. "We are just now introducing this quarter the new user experience that will make it easy to use for new designers. Our technology has been proven."
The Blue Pearl Software Suite, including modules for design analysis, SDC generation, and validation with the new Visual Verification Environment, is available in the first quarter of 2011. Pricing per module starts at $20,000.