There’s a lot to wrap our brains around here, so before we plunge into the fray, let’s take a moment to remind ourselves as to who Tabula are and what they do. Let’s start with the fact that Tabula is a new FPGA company; also that it has an absolutely outstanding management team. Founder and chief technology officer (CTO), Steve Teig, has been the CTO of four other successful start-ups, and was also CTO at Cadence Design Systems. Tabula's chief executive officer (CEO), Dennis Segers, was CEO at Matrix Semiconductor (which was a pioneer in 3D memory ICs) and "the father of Virtex FPGAs" at Xilinx. And the rest of the team read like the "Who's Who" of FPGA space – they even have a "token Altera guy" (Alain Bismuth, who used to be the vice president of HardCopy ASICs at Altera).
Next, let’s remind ourselves as to Tabula’s ABAX 3D FPGAs. I should point out that the folks at Tabula refer to these as ABAX 3PLD devices, but I will always think of these as FPGAs (sorry).
Actually, let’s first take a step back and start by considering a conventional "2D FPGA". In this case, about 80 to 90% of the device is consumed by the interconnect, which negatively affects power consumption, performance, and capacity. By comparison, a very simplistic view of Tabula's Spacetime architecture is that they use a smaller piece of silicon that they reconfigure eight times for each user clock beat. These reconfigurations are referred to as "folds".
Regular FPGA (left) versus Tabula 3PLD (right)
For example, let's say that your clock is running at 200 MHz. Inside the ABAX, Tabula will have their own clock running at 1.6 GHz, which means that there will be eight of their clock cycles for each of yours. Now let's consider a logical element like a look-up table (LUT). This can be reconfigured on each of Tabula's clocks, which means that it can be visualized by the user to be eight separate LUTs.
This is why Tabula refer to their Spacetime architecture as being “3D.” As opposed to using a third physical dimension, however, in this case the ‘z’ axis is time. But we’re in danger of wandering off into the weeds. One very important point is that all of the above is completely invisible to the user (maybe I shouldn’t even have mentioned it). Having said this, another important point is that, depending on how you manipulate the folds, you can boost up the performance of your logic from 200 MHz to 400 MHz, or 800 MHz, or even 1.6 GHz. This is a tradeoff between capacity and performance, but the exciting thing is that you don’t have to do it for the entire chip – you might have the majority of your logic running at 200 MHz, but have selected portions running at higher clock frequencies.
Now your knee-jerk reaction to this concept of folds might be something along the lines of: "Cool, we only need to use 1/8 of the silicon." In reality, however, we need to store the eight different configurations associated with the eight folds. The bottom line is that – when everything is taken into account – Tabula's Spacetime fabric ends up consuming only about 1/3 the silicon real-estate of a regular 2D FPGA of the same capacity. Furthermore, the tracks in the Spacetime fabric are 78.5% shorter than in a regular FPGA, which means that everything is much more routable and timing closure is much, much easier.
The end result is that we (well, Tabula) can either use this Spacetime fabric to achieve the same capacity as a regular FPGA with only 1/3 of the silicon ... or we can use the same amount of silicon as the regular FPGA to achieve a much higher capacity. Speaking of which, take a look at the ABAX family:
Observe that all members of the family have the same number of general-purpose I/O pins (920), the same amount of on-chip RAM (5.5 megabytes … that’s bytes, not bits!), and the same number of high-speed SerDes channels, all of which means that it’s easy to swap one member of the family for another. The main difference is in the number of look-up-tables (LUTs), which range from 220,000 to 630,000; also the largest member of the family contains 1,280 18 x 18 multiplier-accumulators.
The big point to notice here is the price: the smallest part costs only $105 while the Big Kahuna of the family – the ABAX A1EC06 – is only $200, which is a fraction of the cost you would expect to pay for a high-capacity, high-performance device from other FPGA vendors. As you can imagine, these devices are going to be of tremendous interest in the communications, industrial, medical, test, and military/aerospace industries, but we digress...
Today’s hot-off-the-press news is that the folks at Tabula have just announced the availability of their Stylus
design software for their ABAX family of 3D Programmable Logic Devices (3PLDs).
This totally integrated synthesis and place-and-route (SP&R) package manages the underlying reconfiguration transparently, automatically mapping standard RTL into the Spacetime fabric. In addition, it combines leading-edge synthesis technology with 3D, timing-driven, place-and-route within a flow and methodology that are familiar to FPGA and ASIC designers, thus requiring little or no learning curve.
Supported by a browser-like GUI, Stylus offers an intuitive, familiar design environment for ASIC and FPGA designers. At the heart of Stylus is Spacetime-optimized synthesis coupled with timing-driven 3D place-and-route. Stylus enables designers to realize all of the benefits of 3D by automatically and transparently mapping standard RTL directly into Spacetime. Stylus accepts standard VHDL/Verilog/System Verilog inputs as well as SDC constraints.
In another industry first, Stylus’ integrated GUI links logical, physical, and schematic project views, giving developers the ability to analyze all aspects of a design together. Several productivity-enhancing features have been implemented, including advanced floor-planning, static timing, and power analysis. In addition, Stylus provides on-chip debug capabilities by supporting the integration of debug logic and direct probing of select nodes in a user circuit. Stylus offers seamless integration of soft IP cores from Tabula’s IP partners, and supports design libraries for industry-standard logic simulators.
Cloud Computing – The way modern software is delivered
Of particular interest is that the folks at Tabula have created and deployed Stylus in a cloud-computing environment to ensure that designers always have access to the latest software without either the overhead associated with IT management or the expense of compute servers.
Access of the cloud through the Web not only increases productivity but also enhances the users’ experience by enabling real-time, on-site-like, technical support. Meticulously developed with security and privacy in mind, Tabula Compute Cloud keeps each customer’s data separate and secure via best-in-class processes and technologies.
STOP! I hope you didn’t skip over this cloud stuff, because this is HUGE!!! Having Stylus running in the cloud means that you don’t have to install the software on your own machines and that you always have access to the latest and greatest version. (Having said this, the folks at Tabula tell me that all software versions will be maintained in the cloud, so you can continue working with an earlier version of you so desire.)
And think about the support angle. If you do bump into a problem you can get one of Tabula’s AE’s to watch over a run with you. This is a huge productivity booster – from the user’s perspective it’s like having 24/7/365 onsite support without having to pay for it; from Tabula’s perspective it allows a small company to provide a level of support that is usually associated only with major corporations (who would charge you through the nose).
One last point is that driving the software is machine independent – theoretically you could even use your smartphone to setup and launch a new run before boarding an airplane (once you’ve launched a job you can disconnect and leave it running and reconnect later).
This is all very, very cool – I’m hoping to persuade the folks at Tabula to write a “How To” design article that walks us through the whole thing step by step (won’t they be surprised when they get to read this part?).
Pricing and availability
Stylus is immediately available free of charge to Tabula customers: please visit www.tabula.com/tools/stylus.php