Actually I heard that their income was up 53% in 2010 compared to 2009, which was significantly higher than the 40% increase enjoyed by the programmable logic market as a whole.
It just seems to me that the guys and gals at Lattice are on a roll – they seem to be doing a lot of things right – and that includes today's announcement about the release of their HDR-60 Video Camera Development Kit. This is a production-ready High Definition (HD) video camera development system based on the LatticeECP3 FPGA family.
Pre-loaded with a plug and play evaluation Image Signal Processing (ISP) pipeline based on Intellectual Property (IP) Cores from Lattice partner Helion GmbH, the Kit works right out of the box. The IP is capable of delivering 1080p performance at 60 frames per second with 2D noise reduction and High Dynamic Range (HDR). Designed with a form factor to fit into commercially available camera housings and capable of supporting two sensors simultaneously, the Kit enables rapid evaluation and prototyping of high-definition HDR video cameras for security and surveillance, traffic control, video conferencing and automotive applications. Schematics and layout files are available free to all purchasers, further accelerating time to market.
The Lattice HDR-60 Video Camera Development Kit is priced at $399. Before we go further, you might wish to check out the following video on YouTube:
About the Lattice HDR-60 Video Camera Development Kit
The Lattice HDR-60 Video Camera Development Kit has been designed using a LatticeECP3-70 FPGA; however, the ISP IP pipeline needed to implement a complete 1080p60 HDR camera requires only a 33K LUT LatticeECP3-35 device. The Development Kit offers camera manufacturers several unique benefits, including a fully integrated HDR image signal processing pipeline from sensor to HDMI/DVI display.
Equipped with an Aptina 720p HDR sensor, with a 1080p HDR sensor planned in Q2 2011, the Kit also offers the industry’s fastest auto-exposure, greater than 120dB system dynamic range, a highly efficient Auto White Balance algorithm and 2D noise reduction – all in streaming mode through the FPGA without the need for an external frame buffer, enabling extremely low latency and further reducing system cost. On-board DDR2 memory also enables applications such as 3D noise reduction, image stitching from multiple sensors, image rotation and de-warping.
As an example, consider the image shown below. This is the way the development kit demo works out of the box – you literally connect the board to the power supply and the monitor and you're up and running. What they've done is to take the entire image captured by the camera, chopped it in half, and replicated one of the halves. On the left-hand side we see the version without all of the image processing algorithms – what happens is that the bright light in the scene tends to wash everything else out with regard to color, contrast, and so forth. By comparison, on the right-hand side we see the same image with all of the image processing algorithms performing their magic – you have to admit that this is rather impressive.
In addition to two USB ports, the Kit features a RJ45 Ethernet port, a Broadcom Broadreach PHY and a built-in BNC connector, offering support for Ethernet over RG6 coaxial cable for distances up to 700 meters at 100Mbps for customers incorporating compression encoders into their designs. The Development Kit also supports easy programming over standard low-cost USB cable.
“The Lattice HDR-60 Video Camera Development Kit enables us to accelerate our camera design cycles and gives us significant advantages in time to market,” said Tian Guang, Chief Technical Officer of BOCOM Digital Technology, a leading innovative products and solution provider in urban surveillance, ITS and telematics systems in China. “The image quality and HDR performance offered by the IP are of a very high order, while its small footprint, fitting inside a LatticeECP3-35, allows us to offer our customers high quality, truly differentiated HD cameras with HDR at very low system cost.” For more information about BOCOM, please visit www.bocom.cn.
The pre-loaded, production ready evaluation camera reference design included with the Kit is future-proof, containing IP capable of being parameterized to support sensors up to 16 megapixels to protect the customer’s investment. In addition to the on-board HDR ISP pipeline reference design, the Kit is supported by a comprehensive ISP library. The ISP IP is available for licensing either standalone or bundled with devices from the award-winning, low-power LatticeECP3 FPGA family, depending on customer requirements.
“Our goal with the Lattice HDR-60 Video Camera Development Kit is to enable camera manufacturers to jump start their FPGA-based high definition camera programs by providing a high quality HDR Video Camera reference design engineered to minimize system BOM, while addressing both legacy infrastructure and future-proofing the customer’s investment,” said Niladri Roy, Senior Manager of product marketing at Lattice Semiconductor. “With full 1080p60 support and the ability to scale up to 16MP sensors, as well as support for Ethernet over coaxial cable, the Lattice HDR-60 Development Kit offers nearly twice the functionality at less than half the price of any comparable kit currently available.”
Video demonstrations of the HDR Video Camera Development Kit can be viewed as follows:
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.