I just heard from the folks at Atrenta, providers of SoC Realization solutions for the semiconductor and electronic systems industries, that they are announcing a comprehensive textbook on RTL design. The textbook, Principles of VLSI RTL Design, A Practical Guide, authored by Sanjay Churiwala and Sapan Garg is being published by Springer Science+Business Media.
The book is based on the authors’ experiences while working at Atrenta’s Noida, India R&D center.
“Through our years of work at Atrenta, we had seen a lot of designs and design methodologies. We developed a good understanding of what best practices looked like,” said Sanjay Churiwala. “It was gratifying to be able to put all those ideas down on paper so others can benefit from our experiences.”
The book targets RTL designers and is said to provide rich information on design practices and how they affect downstream implementation tasks. Topics discussed in the text include: reliable RTL construction, clock domain crossings and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling and routing congestion.
“The decisions made by RTL designers can have a profound impact on the schedule and ultimate quality of the chip,” said Sapan Garg. “Through the use of many examples, we highlight how the RTL designer can heavily influence the outcome of any design project.”
The book is available now through Springer.com or at Amazon.com.