Veridae Systems today announced Certus, a multi-FPGA ASIC prototyping validation and debug suite. When paired with a user’s choice of prototyping hardware, partitioning flow, and FPGA CAD tools, Certus provides the key enabling technology of a complete, easy to implement, and best-in-class prototyping solution. Certus is fully tested and available now, and will be demonstrated next week at the Design Automation Conference, Veridae booth 3212.
Verification and validation engineers want to see a complete ASIC design functioning at close to full speed and with real I/O. Until now, the view of the design has been splintered into the individual FPGA views by available debug tools. Certus solves this challenge by providing a single, fully synchronized view across all of the FPGAs and all of the clock domains, giving users the true ASIC design perspective of the prototype environment for the first time.
“Certus is a significant addition to our design flow, and has the potential to greatly accelerate debug,” said Dave Garau, ASIC prototyping and validation manager at Teradici. "The software is easy to use and implement, and outperforms existing solutions by a considerable margin.”
When debugging ASIC prototypes, conventional debug and verification solutions now require long cycles of synthesis, and place and route software run times. Certus enables signal selection and high-speed trouble shooting without running synthesis and routing for every change. As a result, engineers can quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly move ASIC designs into production.
“Certus was designed by IC designers aiming to solve the challenges associated with prototyping, debug and verification of today’s faster, more integrated FPGA-based systems,”
said Jim Derbyshire, Veridae’s chief executive officer. “We are quite pleased with the customer feedback. Early adopters have helped us tune Certus to being an ideal solution for customers seeking best-in-class tools to reduce both prototyping time and ASIC time to market.”
The Certus Suite for FPGA prototyping provides a synchronized view of the entire system, including serial I/O, busses, software code and FPGA hardware. Certus does not require custom connectors or I/O resources and can be deployed on all existing platforms. The suite is based on Veridae’s proven set of software tools that includes the Implementor, which helps to design and implement minimized on-chip signal capture probes quickly and efficiently; the Analyzer, which manages the captured data; and the Investigator, which relates the information back to the design, interpolates the data and displays a larger signal set. The combination of these tools allows designers to have a single synchronized view for faster FPGA-based system validation and debug without endless re-synthesis and place and route.
Certus is available now from Veridae Systems