Digital Blocks is a developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, and FPGA developers with Embedded Processor and Peripherals, Networking, Display Controller, Display Link Layer, 2D Graphics, and Audio / Video processing requirements.
The folks at Digital Blocks have just announced their DB9100 BitBLT / 2D Graphics Engine synthesizable RTL Verilog IP Core family. The DB9100 Graphics Engine IP complements Digital Blocks’ DB9000 family of TFT LCD Controller IP Cores providing a system-level solution to graphics display applications development centered around ASIC, ASSP, and FPGA components.
The DB9100 BitBLT Graphics Engine provides 256 Raster Operations on 3 sources of frame buffer data for Block Transfers with an array of available Bitmap and 2D Graphics operations. The high performance 2D Graphics Engine renders Line, Polygon, and Polygon Block Fills.
DB9100 Family of BitBLT Graphics and 2D Graphics IP The DB9100 family supports the AMBA AXI4, AXI, AHB, and Avalon Bus fabrics. The AXI4, AXI, and AHB fabrics support ASIC and ASSP integrated circuit design teams. The AXI4 supports Xilinx FPGAs. The Avalon supports Altera FPGAs. The DB9100 is tuned to the unique capabilities of each fabric to maximize capability and performance.
The DB9100 comes with a Graphics API Reference Design.
Price and availability
The DB9100 is available immediately in synthesizable Verilog, along with a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please go to Digital Blocks at www.digitalblocks.com
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