When you are trying to digitize a modulated RF signal, you have several choices: you can heterodyne the signal down to a lower intermediate frequency (IF) one or even twice, then digitize; you can heterodyne it directly down to baseband (zero-IF); or you can try to digitize it directly at its carrier frequency. The latter offers the potential to eliminate many signal-chain components, but places stringent, difficult demands on the analog/digital converter (ADC).
Attacking this challenge, the ADC12Dxx00RF family of 12-bit converters from National Semiconductor Corp. comprises a pin-compatible family, featuring conversion rates from 1.0 to 3.6 Gsps, while handling signals beyond 2.7 GHz. These specifications make it a fit even for direct RF-sampling of 3G/4G base stations, and an enabler of high-end SDR (software defined radio) designs. Simplifying signal processing, it enables sampling into—and beyond—the 7th Nyquist zone. The converters can be configured for interleaved or dual-channel modes, for I/Q demodulation.
This converters—which the vendor says are the first to achieve direct RF-sampling beyond 2.7 GHz—can eliminate approximately 20 components usually associated with the channel, while reducing overall power consumption and board-space requirements. (They are also footprint-compatible with National's existing ADC12D1x00 and ADC10D1x00 families.)
The five converters being released are:
The ADC12D1800RF, which provides interleavedsingle-channel sampling rates up to 3.6 Gsps, ordual-channel rates up to 1.8 Gsps, with IMD3 of -64 dBc at 2.7 GHz; noise floor -155 dBm/Hz, and 4.4 W dissipation. (More information is available at http://www.national.com/pf/DC/ADC12D1800RF.html.)
The ADC12D1600RF, which provides interleavedsingle-channel sampling rates up to 3.2 Gsps, ordual-channel rates up to 1.6 Gsps, with IMD3 of -70 dBc at 2.7 GHz; noise floor -154.6 dBm/Hz, and 4.0 W dissipation (See http://www.national.com/pf/DC/ADC12D1600RF.html.)
The ADC12D1000RF, which provides interleavedsingle-channel sampling rates up to 2.0 Gsps, or dual-channel rates up to 1.0 Gsps, with IMD3 of -69 dBc at 2.7 GHz; noise floor -154 dBm/Hz, and 3.5 W dissipation. (See http://www.national.com/pf/DC/ADC12D1000RF.html.)
The ADC12D800RF, which provides interleavedsingle-channel sampling rates up to 1.6 Gsps, or dual-channel rates up to 800 Msps, with IMD3 of -71 dBc at 2.7 GHz; noise floor -152.2 dBm/Hz, and 2.5 W dissipation. (See http://www.national.com/pf/DC/ADC12D800RF.html.)
The ADC12D500RF, which provides interleavedsingle-channel sampling rates up to 1.0 Gsps, ordual-channel rates up to 500 Msps, with IMD3 of -69 dBc at 2.7 GHz; noise floor -150.5 dBm/Hz, and 2,0 W dissipation. (See http://www.national.com/pf/DC/ADC12D500RF.html.)
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.