Imperas has released its models of the Cortex-A9 MPCore and Cortex-A5 UP ARM processor cores, including the 1, 2, 3, and 4-core versions of the Cortex-A9 MPCore. Models of the Cortex-A9 MPCore and Cortex-A5 UP are now available from Open Virtual Platforms (OVP), including example virtual platforms incorporating the cores and support for the cores in Imperas' advanced software development tools.
Imperas earlier this week announced the interoperability of its OVP Fast Processor Models and advanced software Multiprocessor/Multicore Verification, Analysis and Profiling (M*VAP) tools with the Cadence Virtual System Platform. Imperas also announced the development of the OVP Fast Processor Model of the Xilinx MicroBlaze soft processor core. This model of the Xilinx MicroBlaze will be available with certain versions of the Zynq-7000 EPP Virtual Platform as an extension to the virtual platform.
The OVP Fast Processor Models and example platforms are available from the Open Virtual Platforms website, Cortex-A web page. The models of the ARM Cortex-A9 MPCore and Cortex-A5 UP, as well as models of the other ARM processors including the ARM7, ARM9, ARM10, ARM11, Cortex-A and Cortex-M families, work with the Imperas and OVP simulators, and have shown exceptionally fast simulation performance of hundreds of millions of instructions per second. The OVP Fast Processor Models include support for both the 32 and 16-bit instructions, as well as the MMU, MPU, TCM, VFP and NEON features.
Open Virtual Platforms, with over 75 Fast Processor Models, has become the de facto source for instruction-accurate models of processor cores. All OVP Fast Processor Models are instruction-accurate and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle.
OVP processor models employ a state-of-the-art, just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models. The native TLM-2.0 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.
In addition to working with the OVP simulator OVPsim, the OVP Fast Processor Models work with the Imperas Multiprocessor/Multicore/Multithread Software Development Kit (M*SDK). These advanced tools for multicore software verification and analysis include key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot spot profiling, code coverage and memory and cache analysis. The M*VAP tools utilize the Imperas SlipStreamer patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.
The following specific models are available as open source from OVP:
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