Emulators based on standard parts (FPGAs) have some big advantages and disadvantages. The disadvantages are dealing with the constraints imposed by the devices. The advantages relate to the fact that someone else is doing all the chip development and you can just use all of their work in the creation of biggest, better, faster emulation products. Such is the case with the latest announcement by EVE who has released their first emulation products based on the Xilinx Virtex6-LX760 FPGAs. They call it the ZeBu-Blade2. As with all FPGA generations, these new devices bring the cost per emulated gate down, capacities up and an increase in performance.
EVE claims this for the new device: up to 40 megahertz (MHz) and 18- or 32-million ASIC gates depending on the board chosen which could have either 5 or 9 FPGAs. These new devices are single user emulators and EVE states that they can handle more than 70% of current ASIC designs, per usage surveys that they conducted. It can be deployed in co-emulation with hardware description language (HDL), C, C++, or SystemC-based cycle-level or transaction-level testbenches, or in emulation with synthesizable testbenches and in-circuit-emulation (ICE) driven by target systems. For ICE mode, 600 non-multiplexed and voltage programmable I/O pins are available.
The compiler can handle up to 16 asynchronous primary clocks and according to their release unlimited derived clocks using clock-tree routing algorithms that prevent timing violations. This device can use the family of transactor models that are in the EVE library and they are also supplying two configurations: Hardware Development Platforms (HDP) and Software Development Platforms (SDP) to trade off hardware debugging capabilities, not necessary when validating embedded software, at half the cost.
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