Digital Blocks, a developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC), ASIC, ASSP, and FPGA developers with Embedded Processor and Peripherals, Networking, Display Controller, Display Link Layer, 2D Graphics, and Audio / Video processing requirements, today announces six IP Core additions to the Video Signal and Image Processing family.
Digital Blocks’ Video Signal and Image Processing IP Core Family includes the following:
DB1800 - Standard Definition NTSC/PAL/SECAM Video Sync Separator
Digital Blocks’ DB1800 Video Sync Separator IP Core extracts timing information from a standard NTSC/PAL/SECAM composite sync video signal, extracting horizontal sync, vertical sync, chroma burst / back porch, and field 1 (odd) or field 2 (even) detection.
DB1810 - Color Space Converter
Digital Blocks’ DB1810 Color Space Converter IP Core transforms three color components between 10+ color spaces.
DB1820 - Chroma Resampler
Digital Blocks’ DB1820 Chroma Resampler IP Core down converts 4:4:4 Y’CbCr to 4:2:2 Y’CbCr in accordance with the ITU-R BT.601 standard requirements. Includes image rejection filter.
DB1825 - RGB to Y’CbCr Color Space Convert with 4:4:4 to 4:2:2 Chroma Resampler
Digital Blocks’ DB1825 Color Space Converter & Chroma Resampler IP Core transforms 4:4:4 sampled RGB color components to 4:4:4 Y’CbCr color space followed by Chroma Resampling to 4:2:2 Y’CbCr color components (combined DB1810 and DB1820 products).
DB1830 - BT.656 Encoder
Digital Blocks’ DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC & PAL video ITU-R BT.656 digital coding standard.
DB1840 - BT.656 Decoder
Digital Blocks’ DB1840 CCIR 656 Decoder IP Core decodes a ITU-R BT.656 digital framed signal into 4:2:2 Y’CbCr component digital video with synchronization signals.
DB1892 - RGB to CCIR601/656 Encoder
Digital Blocks’ DB1892 RGB to CCIR 601 / CCIR 656 Encoder IP Core interfaces RGB data along with synchronization signals from a LCD Controller (such as Digital Blocks’DB9000IP, or any LCD display timing and control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.
Price and availability
The Video Signal and Image Processing IP Core Family is available immediately in synthesizable Verilog along with synthesis scripts, a simulation test bench with expected results, installation guide, and a technical user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at www.digitalblocks.com
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