If the truth be told, it's not every day that I have something staggeringly, amazingly, knee-knockingly exciting to relate with regard to programmable space (where no one can hear you scream). So I'm delighted to say that today is one of those "red letter days" where I have some mega-exciting news to share.
But before we plunge headfirst into the fray with gusto and abandon, let's take a step back to briefly set the scene. Over recent months, the folks at Xilinx have been unveiling some very exciting programmable devices. For example, there's the Virtex-7 2000T, which is build using 2.5D technology (four FPGA die mounted on a silicon interposer with ~10,000 connections between adjacent dice, all presented in a single package), and which provides the equivalent of around 20 million ASIC gates. And then there's the Zynq-7000 EPP (Extensible Processing Platform), which features a complete hard core dual ARM Cortex-A9 microcontroller subsystem (with on-chip cache, floating point engines, etc.) along with a host of hard core interface blocks, a full-up hard core dynamic memory controller, and a substantial quantity of high-performance programmable fabric.
The thing is that when most folks see reports of these new devices, they say "Oooh" and "Ahhh" and "Shiny", but they typically don’t spend much time thinking about what it will take to actually capture and verify designs using these little beauties. By comparison, designers experienced in the use of programmable devices may well have raised the odd quizzical eyebrow, thinking to themselves "How in goodness's name are we going to actually use these beasts?"
Well, all is now revealed, because after four years of development and a year of beta testing, Xilinx has just announced its Vivado Design Suite. This new IP and system-centric design environment has been created from the ground up to accelerate design productivity for the next decade of what Xilinx is now referring to as ‘All-Programmable’ Devices.
Vivado tools not only speed the design of programmable logic and IO, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM processing systems, Analog Mixed Signal (AMS), and a significant percentage of intellectual property (IP) cores. With up to a 4x productivity advantage over competing development environments, the Vivado Design Suite attacks the major bottlenecks in programmable systems integration and implementation.“Vivado tools are the culmination of work started by Xilinx engineers in 2008 in response to customers’ needs for more productivity, faster time to market, and the ability to go beyond programmable logic to programmable systems integration. It has been beta tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using our stacked silicon interconnect based Virtex-7 devices for extreme capacity and bandwidth,”
said Xilinx Senior Vice President of Platforms Development, Victor Peng.The Vivado design environment
The Vivado Design Suite provides a highly integrated design environment (IDE) with a completely new generation of system-to-IC level tools
, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the user’s needs. Xilinx architected Vivado tools to enable the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.
To address integration bottlenecks
, the Vivado IDE includes electronic system level (ESL)
design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.
To address implementation bottlenecks
, Vivado tools include a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a ‘cost’ function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. Finally, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.“The combination of the Vivado Design Suite and the Virtex-7 2000T FPGA has created a paradigm shift in the programmable logic industry. Vivado has enabled Broadcom to design with the industry’s highest capacity FPGA without any manual floorplanning or partitioning,”
said Paul Rolfe, Manager, Hardware Development Engineering, Broadcom Europe. “We are impressed with the innovation that Xilinx is delivering both in silicon and software.”Availability
The Vivado Design Suite version 2012.1 is available as part of an early access program. Customers should contact their local Xilinx representative. Public access will commence with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 EPP support later in the year. ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to IDS at no additional cost. The ISE Design Suite will continue to be supported by Xilinx for customers targeting 7 series devices and prior generations. To learn more, please visit www.xilinx.com/design-toolsEditor's Note: There really is so much here that a single column simply cannot do it justice. With
Vivado, for example, high-level synthesis (HLS) is no longer a technology that is available only to tier-one design houses who can afford the eye-watering price tag that typically accompanies these tools. My understanding is that Xilinx is pricing this as a $2000 option, which is a fraction of the price of equivalent systems used for ASIC/SoC designs. Suffice it to say for the moment that I think we will be seeing a whole lot of Vivado-related topics over the weeks and months to come.
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