I just heard from the folks at Synopsys about their successful collaboration with Samsung Electronics on the implementation of an ARM Cortex-A15 MPCore processor.
Now I'm interested in this sort of thing – the tools and techniques used to create System-on-Chip (SoC) devices – but I also understand if you are more interested in off-the-shelf processors, in which case you need read no further. The thing is that when I hear about an ARM Cortex-A15 MPCore processor running at GHz+ speeds, I can’t help but say "Oooooh, Shiny!" to myself.
Anyway, this processor core was implemented by the Samsung Austin Research Center (SARC) using Synopsys IC Compiler place-and-route technology, which is a cornerstone of the Synopsys Galaxy Implementation Platform. Running at operating speeds in excess of a gigahertz on Samsung's 32nm low power process, the hardened core has already been deployed in the industry's first Cortex-A15 processor-based SoC for mobile computing devices.
The folks at Synopsys say "The high speed was enabled through a unique combination of innovative optimization techniques and differentiated high-performance technologies which have made IC Compiler the tool of choice for high-performance designs across multiple process nodes."
"Our mission is to deliver the highest frequency while minimizing power for high-end processor and graphics cores targeted to the mobile computing and digital home markets," said Keith Hawkins, vice president, SARC. "Globally, this was the first production tapeout of a Cortex-A15 processor and we relied exclusively on IC Compiler and the Galaxy tool suite to predictably achieve our performance and power targets."
Samsung fabricated the three-million-instance, dual-core Cortex-A15 processor on a 32LP high-K metal gate (HKMG) process. Synopsys collaborated closely with SARC on an implementation methodology based on key high performance technologies and optimization techniques in the Galaxy Implementation Platform to meet Samsung's stringent mass production criteria for an on-time tapeout.
The processor core relied on Physical Datapath in Design Compiler Topographical and IC Compiler for the structured placement of registers to meet power and area objectives. Layout-based debug with Design Compiler Topographical allowed quick analysis of library, netlist, and placement issues to close timing. Clock mesh in IC Compiler and PrimeTime provided the low skew and increased on-chip-variation (OCV) tolerance necessary for the high-performance core.
"Samsung is a leading provider of silicon in the mobile computing market, as can be seen by its smart phone and tablet market penetration," said Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. "Being at the forefront of next generation mobile products, Samsung has driven many of the technology innovations that have reinforced the position of IC Compiler as the leading choice for high-performance design. The benefits of our ongoing partnership can be seen in the impressive level of performance delivered by this gigahertz-plus processor core."
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