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MIPS introduces new Aptiv generation of processor cores

5/10/2012 09:47 PM EDT
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Max The Magnificent
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re: MIPS introduces new Aptiv generation of processor cores
Max The Magnificent   5/18/2012 8:48:10 PM
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This seems a tad uncalled for -- MIPS is an IP company (not a chip company) and as such this announcement is about introducing IP cores, which -- by their very nature -- will take some time to end up in silicon. This announcement is no different to any other IP core launch that MIPS (and their competitors) have done in the past...

jg_
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re: MIPS introduces new Aptiv generation of processor cores
jg_   5/18/2012 9:21:35 AM
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Wow, missing from all the hoopla, is any mention of real silicon, or who the early adopters who are sampling devices right now are ? Availability of real devices is a better milestone. One would almost think they were keen to talk up a stock price ?

Mark.Throndson
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re: MIPS introduces new Aptiv generation of processor cores
Mark.Throndson   5/16/2012 5:31:27 AM
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My earlier response was not meant to imply cores running at different voltages and frequencies at the same time within a single cluster. I was just trying to keep the answer as concise as possible. To elaborate a bit further, the core groups would be implemented to different operating points (high performance and low power implementations), but the groups would not be “on” at the same time, with one exception - a common transition frequency that both core groups are capable of operating at. Under those guidelines, there isn’t a need for the coherence interconnect/L2$ to deal with connecting to multiple cores running at different speeds at the same time. You can imagine that with all cores being based on the same microarchitecture and running at the same frequency within one coherent cluster with one L2$, the transition process from low power to high performance core groups (or vice versa) is relatively straightforward.

BJameson
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re: MIPS introduces new Aptiv generation of processor cores
BJameson   5/15/2012 8:06:55 PM
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The comment on "high performance and lower power core groups within a single coherent multi-core cluster" implies that the cores can be run at different voltages and frequencies at the same time. Is this the case, or is additional customization required by a licensee to enable this? It would seem that enabling the cores to run at different frequencies would require bridges between the cores and the L2 that would increase latency above what is listed in the product description. It sounds like what is being described here are features and specs, some of which are mutually exclusive. Kind of like, "you can have high performance, or power scalability, but not both." Would be good to clarify this point.

Mark.Throndson
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re: MIPS introduces new Aptiv generation of processor cores
Mark.Throndson   5/14/2012 9:56:19 PM
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With the proAptiv family, MIPS is providing top performance very efficiently in one CPU core design. This delivers inherent benefits for low power system design. Designers should evaluate whether using simpler DVFS and multi-core clock/voltage gating techniques with an efficient core can meet system power budget goals before expanding to more costly dual architecture schemes such as “big.LITTLE” (more core license fees and more cost per silicon). That said, if a big.LITTLE type low power scheme is desired, an efficient single core architecture can be used with synthesis/implementation variation within a process node to deliver both high performance and low power core groups within a single coherent multi-core cluster. Because it is the same processor core - just implemented to two extremes - there are no architecture compatibilities to worry about, no performance “divots” during transitions between two different microarchitectures, and a less complex and lower cost implementation due to one shared coherence manager and L2 cache. As to the question about engineering design costs, if you assume that all design teams are trying to implement a good design, two designs will take a lot more engineering effort than one.

chrmjenkins
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re: MIPS introduces new Aptiv generation of processor cores
chrmjenkins   5/11/2012 2:59:45 PM
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While these new cores look impressive, MIPS has a huge hill to climb to even scrape at the level ARM is in the embedded market. Also, kudos to their marketing team taking a dig at everything ARM touts about Eagle and looking forward. However, I don't think big.LITTLE counts as exotic. It's a pretty intuitive jump given the space's needs. Why spend so much engineering effort making one design fit all needs when you can easily produce two and let the customer decide?

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