The folks at Lattice Semiconductor have released a serial sub-LVDS bridge design to support the Sony IMX136 and IMX104 image sensors. The serial sub-LVDS format is expected to become Sony’s primary image sensor interface for embedded/industrial users.
This new image sensor bridge design utilizes the low cost, low power Lattice MachXO2 PLD (programmable logic device) to interface to the serial sub-LVDS bus of the Sony IMX136 or IMX104 image sensor. Applications that can benefit from this design include surveillance cameras, video conferencing and industrial cameras. This image sensor bridge design allows an ISP (Image Signal Processor) with a CMOS parallel interface bus to connect to the Sony IMX136 or IMX104.
The MachX02 "Do-It-All" PLD
The Lattice MachXO2-1200 device interfaces directly to the sub-LVDS I/Os and no external discrete components are required. The image sensor bridge application can support 1080P60 resolution with a 12-bit ISP interface. If customers desire the full 1080P120 capability of the Sony IMX136 or IMX104, then the design code in the MachXO2 device can be modified easily to accommodate this. The image sensor bridge design is available now for download, and the MachXO2-1200 is in full production. Click Here
to obtain the Sony IMX136 or IMX104 serial image sensor bridge design files.“The Sony serial sub-LVDS bridge design is the latest addition to our constantly growing camera design ecosystem,”
said Kambiz Khalilian, Lattice Strategic Marketing Manager for Cameras & Displays. “We are pleased to offer this image sensor bridge design so customers can quickly introduce cameras based on the Sony IMX136 and IMX104. This latest bridge design further demonstrates Lattice’s leadership in partnering with key ISP and image sensor companies.”
If you found this article to be of interest, visit Programmable Logic Designline
where – in addition to my Max's Cool Beans
blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).