Allegro packs a bunch of new capabilities into this new release hoping to accelerate timing closure for high-speed interfaces by 30-50 percent, through timing-aware physical implementation and verification within an electrical CAD (ECAD) team collaboration environment for PCB design using Microsoft® SharePoint® technology. I know that is quite a mouthful, but we can divide it down into the capabilities to address each piece of that.
First it accelerates timing aware physical implementation through Auto-interactive Delay Tuning (AiDT). Auto-interactive Delay Tuning lessens the time to meet timing constraints on advanced standards-based interfaces, such as DDR3, by 30-50 percent. AiDT allows users to rapidly adjust the timing of critical high-speed signals on an interface-by-interface basis, or apply it at byte-lane level, reducing the need to tune the traces on a PCB from days to hours. The EMA Timing Designer, integrated with the Allegro PCB SI capability, helps users quickly achieve timing-closure on critical high-speed signals.
A design teams become more geographically distributed and with increased outsourcing, there is an increasing need for product lifecycle management and block-level sharing. For this Cadence has performed an integration with Microsoft SharePoint 2010 that provides a scalable solution from desktop to cloud.
16.6 comes with enhanced miniaturization capabilities for embedding dual-sided and vertical components, timing-aware physical implementation and verification that accelerate timing closure, and improved ECAD and mechanical CAD (MCAD) co-design — all crucial for accelerating development of feature-rich electronic products.
PCB design miniaturization capabilities were first introduced in 2011. This release continues to support the latest manufacturing advances in embedding active and passive components in a PCB to address the specific design requirements associated with ever shrinking board size. Components can now be embedded vertically on an inner layer of a PCB leveraging the Z-axis, which greatly reduces X- and Y-axis real estate on the board.
PCB/enclosure co-design is streamlined through an ECAD-MCAD flow based on EDMD schema version 2.0, a proStep iViP standard. This flow reduces unnecessary iterations between ECAD and MCAD teams shortening time for product creation.
I am sure I missed some of the other new capabilities but more information should be available on their website www.cadence.com/products/pcb/pages/whatsnew.aspx
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