As you may recall, last year the folks from MathWorks hosted two joint webinars with Altera on topics related to FPGA design.
Well, I was excited to hear that the little scamps have a new webinar coming up, titled Verifying Altera Floating-Point IP Cores on FPGAs with MATLAB & Simulink.
In this webinar, the guys and gals from MathWorks will we show how to use their HDL Verifier product to verify a rather novel IP core: a Cholesky decomposition, implemented in floating-point using Altera Cyclone IV and Stratix IV devices. This is one of the Altera cores that BDTI evaluated in a study last year.
They say that they will be showcasing the use of their “FPGA-in-the-loop” feature with a series of demos that show designers how to take third-party IP – in this case, from Altera – and to use a system-level testbench in Simulink.
The webinar’s registration page can be found as follows:
I look forward to seeing you there :-)
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