As design geometries get smaller, new manufacturing defects emerge and these require better tools to try and get around them or better ways to test and repair those where local variations and fluctuations in doping can create small areas of sub-optimal silicon. Many of these defects are first brought to light with memory designs that tend to adopt the new technologies faster and have such a compact and regular structure. This makes the problems easier to identify and thus provide a good place to start the long process of finding solutions to enable yield ramp.
That was the focus of a recent announcement from Synopsys and the introduction of their DesignWare® STAR Memory System® 5 (SMS) and associated embedded memory test, repair & diagnostics for 20nm and below.
SMS takes on a new hierarchic structure as shown below. First, SMS generates the wrappers around each memory instance. A collection of wrappers connects to a processor which in turn connects to the SFP (Shared Fuse Processor) and JPC (JTAG-to-P1500 converter). That logic, in turn, connects to the JTAG port (through the TAP controller). SMS enables the automated stitching together of the RTL and also create a chip level test bench to verify that they are connected correctly.
The new architecture can provide up to 30% area reduction compared to the previous generation and less routing congestion. In addition design is simplified because the test wrapper does not change the design hierarchy and thus there is no need to modify constraints or UPF description. The solution can also attach to memories contained in processors with no additional BIST muxes.
The advanced diagnostics enable faster fault localization and classification which can help reduce test and repair time as well as enable faster yield ramp.
Brian Bailey – keeping you covered