The folks at Altera and ARM have announced that, with a unique agreement, the companies have jointly developed a DS-5 embedded software development toolkit with FPGA-adaptive debug capabilities for Altera SoC devices.
The ARM Development Studio 5 (DS-5) Altera Edition toolkit is designed to remove the debugging barrier between the integrated dual-core CPU subsystem and FPGA fabric in Altera SoC devices. By combining the most advanced multi-core debugger for the ARM architecture with the ability to adapt to the logic contained in the FPGA, the new toolkit provides embedded software developers an unprecedented level of full-chip visibility and control through the standard DS-5 user interface. The new toolkit will be included in the Altera SoC Embedded Design Suite and will begin shipping in early 2013.
Altera SoC devices combine a dual-core ARM Cortex-A9 processor with FPGA logic on a single device, giving users the power and flexibility to create custom field-programmable SoC variants by implementing user-defined peripherals and hardware accelerators in the FPGA fabric. Altera is currently shipping engineering samples of its Cyclone V SoC devices (Click Here for more details).
The ARM Development Studio 5 (DS-5) Altera Edition toolkit dynamically adapts to unique customer configurations of the FPGA within the SoC to seamlessly extend embedded debugging capabilities across the CPU-FPGA boundary and unify all software debugging information from the CPU and FPGA domains with the standard DS-5 user interface. When combined with the advanced multi-core debugging capability of the DS-5 Debugger, and the link to the Quartus II SignalTap logic analyzer for cross-triggering capability, the toolkit delivers an unprecedented level of debugging visibility and control that leads to substantial productivity gains.
“Disruptive, innovative silicon devices demand equally disruptive and innovative software tools. That demand has been met by this innovative toolkit for Altera 28 nm Cyclone V and Arria V SoC devices and for upcoming Altera 20 nm SoC devices,”
said John Cornish, executive vice president of the System Design Division at ARM. “This technical innovation has unified CPU debugging with FPGA debugging to bolster user productivity. Altera and ARM have made this advanced tool technology with premium, productivity-boosting features widely available through Altera SoC development kits and the Altera SoC Embedded Design Suite. We believe this combination will deliver valuable benefits to our mutual customers.”
The ARM DS-5 toolkit suite offers the most advanced multi-core debugger in the market for the ARM architecture. It supports debugging on systems running in asymmetric multiprocessing (AMP) and symmetric multiprocessing (SMP) system configurations. It is broadly used for board bring-up, driver development, OS porting, bare-metal and Linux application development, through JTAG and Ethernet debugging interfaces, and offers Linux and RTOS awareness.“We are very proud of the partnership and innovation in this joint work with ARM,”
said Vince Hu, vice president of product and corporate marketing at Altera. “The ARM DS-5 Altera Edition toolkit gives software engineers an incredibly powerful development and debugging tool, allowing for the fastest development time for our SoC devices.” Key features and benefits
The ARM DS-5 Altera Edition toolkit features the following capabilities:
Pricing and availability
- Software debug view adapts to include the peripheral devices programmed by the developer into the FPGA fabric, providing a seamless view of both the hard and soft peripheral register memory map of the entire SoC.
- The DS-5 Debugger simultaneously displays debug/ trace data for the Cortex-A9 processor cores and CoreSight-compliant custom logic cores implemented in the FPGA fabric.
- Altera USB Blaster JTAG debug cable supports both the DS-5 debugger and other Altera JTAG-based tools for the Altera SoC device.
- Allows non-intrusive capture and visualization of signal events in the FPGA fabric that can be time-correlated with software events and processor instruction trace.
- Supports advanced, signal-level hardware cross-triggering between the CPU and FPGA logic domains, which enables cross-domain hardware/software co-debugging.
- Includes the DS-5 Streamline performance analyzer, which correlates software thread and event information with hardware counters from both the SoC and FPGA, enabling the identification and correction of system-level bottlenecks.
The ARM DS-5 Altera Edition toolkit for Altera SoCs is being presented at the ARM Technical Symposium in Paris on December 13, 2012. This toolkit will be included in the Altera SoC Embedded Design Suite (Altera SoC EDS) Subscription Edition for $995. The Altera SoC EDS will start shipping in early 2013.
If you found this article to be of interest, visit Programmable Logic Designline
where – in addition to my Max's Cool Beans
blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).