The folks at Digital Blocks, developers of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, and FPGA developers with embedded processor and associated peripherals requirements, have announced the extension of their DB-I2C-MS / DB-I2C-M / DB-I2C-S I2C controller IP core family, with the following enhanced system-level features and integration capabilities:
- CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon / Qsys interconnect fabrics
- DMA transfer between the I2C Bus and Memory (SDRAM / SRAM / FLASH)
- Direct interface to user Registers within ASIC / ASSP / FPGA, for Master/Slave transfer across the I2C Bus
- Remote Configuration of a Digital Blocks’ I2C Slave by an I2C Master
- Enhanced SCL / SDA spike filtering capabilities
- Enhanced Repeated Start capabilities
- Control Unit which completely off-loads the I2C transfer from the CPU
The DB-I2C family contains the usual I2C compliant features: Multi-Mastering, Clock Synchronization, Arbitration, SCL held low by Slave, Repeated Start, 7/10-bit addressing, and General Call capabilities as well as 100 Kbs, 400 Kbps, and 1 Mbps I2C bus speeds.
The DB-I2C IP Core Family is offered as follows:Price and availability
The DB-I2C IP Core Family is available immediately in synthesizable Verilog, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at www.digitalblocks.com
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