I'm sitting on the horns of a dilemma here (and it's not very comfortable, let me tell you). The thing is that the folks at Tabula have developed some mega-cool technology, but they don't really want to talk about it.
That didn’t come out quite the way I intended it to. The point is that the folks at Tabula would much rather talk about the solutions their new ABAX2 3DPLDs (which I will always think of as 3D FPGAs) offer and the applications to which they can be applied.
They are less interested in mentioning little techno-weenie nuggets of information such as the fact that these little scamps (the chips, not the folks at Tabula) are based on a novel fabric called the Spacetime 3D architecture that employs esoteric concepts like "time vias", that they are implemented at 22nm using Intel's advanced 22nm Tri-Gate process, or that everything on the chip – including the programmable fabric – can run at up to 2GHz.
Of course they will mention this if you push them, but then they deftly try to guide you back to what they see as being the most important stuff, which is what you can do with these little rascals.
So here's the deal from their perspective… the folks at Tabula have just announced a comprehensive suite of high-performance packet processing solutions. The suite solves the most challenging problems posed by the transition from 10G to 40G and 100G: specifically, routing of high-performance buses, on-chip RAM throughput, and timing closure for the ultra-high-performance functions required by these systems.
The packet processing solutions, combined with Tabula’s new ABAX2P1 3PLD device (the first of the ABAX2P series), deliver unique capabilities such as the processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G-to-100G bridge. These breakthroughs are enabled by Tabula’s industry-leading technologies in four key areas: 1) Programmable 3D architecture, 2) RTL compiler, 3) leading-edge process technology, and 4) 3PLD devices.
Tabula will demonstrate its high-performance packet processing solutions during the company’s first series of Spacetime Forums, beginning April 8th. This series of one-day technical seminars will continue through May across a dozen cities in North America, Asia, and Europe. Over 250 engineers from key telecom and network system OEMs are expected to attend.“With the migration from 10G to 40G and 100G, FPGA users are having a hard time delivering the kind of throughput needed by these systems,”
said Rich Wawrzyniak, Senior Market Analyst: ASIC & SoC, at Semico Research Corp. “With this set of programmable solutions, Tabula is demonstrating that their 3PLD devices can support four 100G streams on a single programmable device, something not achievable on other programmable solutions.”
The high-performance packet processing reference design suite is composed of:
- A 12x10G-to-100G bridge reference design kit, implementing an aggregation function commonly used in communications systems and using the ABAX2P1 device’s unique high performance bus-handling capabilities.
- A 4x100G switch reference design kit, targeting data center migration from 10G to 40G and 100G, is made possible by the ABAX2P1 device’s ability to process multiple 100G streams.
- A 2nd-generation Ternary Search Engine (TSE) reference design kit, delivering the high-performance search capabilities required for leading-edge routers and NGFW while showcasing the ABAX2P1 device’s unmatched RAM capabilities.
To facilitate user design, the company also delivers a complete set of design examples and soft IP cores tailored for many of the most performance-critical functions found in high-performance packet processing equipment. Examples include a 600Gbps packet classifier, a 100Gbps 64-bit CRC generator, and a 1.3Tbps L2 packet parser.“The capabilities we have demonstrated are simply out of reach of even the most advanced FPGAs,”
said Dennis Segers, Tabula’s Chief Executive Officer. “With this comprehensive suite of programmable solutions, we are uniquely supporting the migration from 10G to 40G and 100G that is currently underway.”Tabula’s four core technology components
- The Spacetime 3D architecture employs time, rather than space, as a third dimension, rapidly reprogramming every resource on the chip to perform multiple, different functions per user cycle – up to 12 in the current generation. Chips using Spacetime, called 3PLDs, are nevertheless presented as having three spatial dimensions with all of their resources distributed across 12 floors or "folds," which dramatically reduces die size vs. FPGAs. In addition, all components in a 3PLD – logic, RAM, multiply/accumulate blocks, and interconnect – operate in concert at up to 2GHz, eliminating the performance bottlenecks that exist in FPGAs.
- The Stylus compiler integrates cutting-edge technologies, such as sequential timing, router-aware placement, and automatic co-optimization of performance and density to offer simpler, more intuitive RTL design and a faster timing closure loop.
- Tabula’s partnership with Intel has provided for the manufacture of the ABAX2P series of devices on Intel’s advanced 22nm Tri-Gate process. The 3D Tri-Gate transistors, the most advanced in the world, provide unmatched speed at low operating voltage for reduced power. Production scalability to meet the highest volume demands is supported via this key alliance.
- The ABAX2P1 3PLD chip is a 12-fold Spacetime device that delivers unique RAM and logic fabric capabilities alongside tailored, hard IP blocks: a combination that makes the chip and future members of the ABAX2P series well-suited for the most demanding packet processing applications.
By leveraging all four of these components, Tabula’s high-performance packet processing suite provides a programmable solution that delivers industry-leading performance and can readily implement even the most challenging communications/network functions.More about ABAX2P1
The ABAX2P1 3PLD device integrates key capabilities that enable system designers to implement high-performance routers, switches, NGFW, and other communication systems. They include:
- A programmable fabric supporting 2 GHz throughput through every component of the chip – logic, RAM, MAC blocks, and interconnect
- 23.3 Mbytes of 12- and 24-port on-chip memory delivering 13.8TB/s of throughput – enough to support multiple 100G streams
- Multiple, built-in, hard, DDR3 controllers operating at 2.133 GT/s, the maximum DDR3 rate, delivering the bandwidth necessary to support external packet buffering or storage of search tables for multiple 100G streams
- Multiple, built-in, hard, 100G Ethernet MACs to ensure easy timing closure and low resource utilization of these ultra-high-performance standard blocks
The initial set of high-performance packet processing solutions is incorporated in Stylus and is available now. Additional suite offerings are scheduled to be released on a monthly basis. Engineering samples of ABAX2P1 will be available in Q3.
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