Digital Core Design (DCD), an IP Core and System on Chip design house from Poland, has introduced its newest I2C Bus Interface soft core for use in ASICs, SoCs, and FPGAs. The DI2CMS is fully compatible with Philips v. 3.0 specification, which means it can operate at Standard, Fast, Fast Plus, and High Speed (up to 3,4 Mb/s). Moreover, The DI2CMS allows master and slave mode, arbitration, and clock synchronization,. It also offers support for multi-master systems, 7-bit and 10-bit addressing formats on the I2C bus, and additional valuable features.
The DI2CMS provides an interface between a microprocessor or microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver, depending on the working mode, which is determined by the MCU. DCD’s IP Core conforms to the latest I2C v. 3.0 specification, implementing features like:
- Master and Slave operation (support for all speeds: Standard, Fast, Fast Plus, and High Speed)
- Arbitration and clock synchronization
- Support for multi-master systems
- Support for both 7-bit and 10-bit addressing formats
- User-defined timings [data setup, start setup, start hold and others]
- Simple interface with support for: AMBA – APB Bus, Altera – Avalon Bus, Xilinx – OPB Bus
- Interrupt generation and more…
The DI2CMS is technology independent – it's presented in VHDL and Verilog RTL that can be implemented in a variety of process technologies. "Based on 14 years’ market experience, we wanted to create an I2C IP Core that will offer maximum functionality,"
says Piotr Kandora, VCEO, Director of R&D at Digital Core Design. "For this reason, the DI2CMS implements almost every possible I2C function, so it can be completely customized in accordance to the customer's needs."
Digital Core Design’s family of I2C IP Cores consists of: DI2CM, DI2CS, DI2CSB, and the DI2CMS mentioned above. Depending on the target application, they can work as a master, slave, base, or master/slave.
FPGA-based deployment of the DI2CMS core.
The DI2CM (I2C Bus controller Master) performs master communication between a microprocessor/microcontroller and an I2C Bus. It allows operations as the I2C master transmitter and the I2C Master receiver. The DI2CS (I2C Bus controller Slave) carries out slave communication between a microprocessor/microcontroller and an I2C Bus. It allows operations as an I2C Slave receiver and an I2C Slave transmitter. And, last but not least, the DI2CSB (I2C Bus controller Slave/Base version) performs communication between an I2C Bus and passive devices, like LCD drivers, memories etc.
Key features are as follows:Click Here
for more information and a data sheet.
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