OK, I have to say that I am seriously impressed. Just to set the stage, I started off designing my first ASIC in 1980 when the state-of-the-art in design tools (at least, the ones that were available to my team) were pencils and paper, which we used to capture gate-level schematics.
Over the years I've seen EDA evolve, with design and verification technologies becoming evermore sophisticated. I remember when the first high-level HDLs appeared on the scene (long before Verilog and VHDL). I remember when language-driven design and the first logic synthesis tools started to appear (and the old designers said "That will never catch on!"). I remember when the first FPGAs became available and we all thought "Well, those might come in handy if we need a simple state machine" (how little we knew).
The first EDA tools I laid my hands on (and this is before we even knew how to spell "E-D-A" – we used to talk about CAE and CAD in those days of yore) employed a command-line interface. I was well-impressed when graphical user interfaces (GUIs) appeared on the scene (I was even more impressed when they started to use color).
So, the bottom line is that I've been around a long time and seen a lot of things. I've seen some really awful design and verification tools; I've seen some really clever and innovative tools; I've even seen really useful tools that actually got the job done; and -- every now and again, once in a blue moon -- I've seen a tool that makes me say to myself "This is something really special that has just raised the bar for the industry."
Last year Xilinx introduced the Vivado Design Suite, which included all sorts of goodies, including high level synthesis (HLS) technology that regular folks could use (and afford) and some really useful IP Packaging technology. Now they've taken things to the next level.
A couple of days ago I saw a live demo that blew me away (you can see a video of this demo below). This demo featured the new Vivado IP Integrator
. When you first see this you think "OK, a block-level graphical interface – I've seen this sort of thing before."
Well, you have and you haven't. First of all, this tool boasts a bunch of high-end features such as inherited properties, which means that if you set the width of a bus in one place, that width flows through the appropriate portions of the data path without you having to do anything.
But there's so much more -- the IP Integrator truly does take things to a new level of sophistication and ease-of-use. There are some "simple" things that are really tasty, like the fact that you can slap IP blocks down on the screen and connect them together in a rather untidy fashion, and then click the "tidy up" button (or whatever it's called), and the system re-draws the diagram to look the way you would have created it if you'd had more time (and skill).
Another deceptively "simple" feature is the ability to start off by creating a "flat" diagram and to later select a number of blocks and click the "Form a hierarchical block" button and for the system to do so. Even better, if you forget something, you can simply drag-and-drop additional IP blocks from one portion of the hierarchy to another.
But where things really start to get clever is when the system informs you of things you've neglected to do, or prevents you from doing something stupid, or advises you of things you can (or should) do.
I really could waffle on about this for ages, but instead I would suggest that you Click Here
to watch a short video demo. I know… I know… we've all seen really clever demos; we all know that it's a lot easier when you are watching an expert who really knows what he or she is doing; and we all know that things are never quite so simple when you are doing it yourself. But when you watch this demo I think you will have to agree that the things you see that take only a few minutes here would actually take you many weeks of effort if you were doing it the "old school" way.
OK, enough of my meandering musings -- take a look at the above demo and then post a comment to this article telling me what you think. Meanwhile, the following is the "official" release from the folks at Xilinx:
Xilinx today announced two major advances in productivity as part of a new major release of the Vivado Design Suite
, the programmable industry’s first SoC-strength design suite. The Vivado Design Suite 2013.1 release includes a new IP-centric design environment for accelerating the time to system integration, and a comprehensive set of libraries to accelerate C/C++ system-level design and high-level synthesis (HLS).Accelerated Time to IP Creation and Integration
To accelerate the creation of highly integrated, complex designs in All Programmable FPGA devices, Xilinx has delivered the early access release of the Vivado IP Integrator (IPI). Vivado IPI accelerates the integration of RTL, Xilinx IP, third party IP and C/C++ synthesized IP. Based on industry standards such as the ARM AXI interconnect and IP-XACT metadata for IP packaging, Vivado IPI delivers intelligent correct-by-construction assembly of designs co-optimized with Xilinx All Programmable solutions. Built on the foundation of the Vivado Design Suite, IP Integrator is a device and platform aware interactive, graphical and scriptable environment that supports IP-aware automated AXI interconnect, one-click IP subsystem generation, real-time DRC, interface change propagation, and a powerful debug capability. When targeting a Zynq-7000 All Programmable SoC
, embedded design teams can now more rapidly identify, reuse, and integrate both software and hardware IP targeted for the dual-core ARM processing system and high performance FPGA fabric. “Vivado has already provided us with a major leap in our productivity for development of reconfigurable computing platforms and applications,”
said Shep Siegel, CTO of Atomic Rules LLC. “The combination of Vivado IPI and 7 series silicon is enabling us to accelerate our development schedules. We are impressed with the innovation that Xilinx is delivering both in silicon and design flows to address our end customer requirements.”
To see a demonstration of the Vivado IP Integrator, please watch this video
.Libraries for Accelerated System-Level Design
To accelerate C/C++ system level design and high-level synthesis (HLS), Xilinx has enhanced its Vivado HLS libraries with support for industry standard floating point math.h operations and real-time video processing functions. Over 350 active users and 1000+ customers evaluating Vivado HLS will now have immediate access to video processing functions integrated into an OpenCV environment for embedded vision running on the dual-core ARM processing system. The resulting solution enables up to a 100X performance improvement of existing C/C++ algorithms through hardware acceleration. At the same time, Vivado HLS accelerates system verification and implementation times by up to a 100X compared to RTL design entry flows. When targeting a Zynq-7000 All Programmable SoC, design teams can now more rapidly develop C/C++ code for the dual-core ARM processing system, while compute intensive functions are automatically accelerated in the high performance FPGA fabric.
To learn more about how Xilinx is staying a generation ahead with Vivado Design Suite, please visit www.xilinx.com/vivado
Download Vivado Design Suite 2013.1 today at www.xilinx.com/download
. For early access to the IP Integrator and new Vivado Design Suite support for Zynq-7000 All Programmable SoCs, contact your local sales team. Sign up for or view online training
for Vivado Design Suite and take advantage of the Vivado Design Suite-based Targeted Reference Design
to jump-start your productivity.
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