The DP8051 is the fifth consecutive realization of the 8051 IP core in Digital Core Design’s portfolio. Like its kinsfolk, the DP8051 is characterized by its simplicity, high efficiency, and high performance. This pipelined RISC architecture executes up to 300 million instructions per second, which means that the DP8051 runs the Dhrystone 2.1 benchmark program 11.46 to 15.55 times faster than competitive cores.
The DP8051 is a high-performance, speed-optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. A broad set of additional features and peripherals let the engineer tailor the core to the specific application and/or hardware requirements.
Moreover, the core has been designed with special attention with regard to its power-to-performance ratio. "This ratio is extended by an advanced power management PMU unit," explains Tomasz Krzyzak, VP, Member Board of Directors at Digital Core Design. "Also, there’s a bunch of serviceable peripherals available, such as 2 to 15 interrupt sources, 4 interrupt levels, 2 data pointers, a USB device, an Ethernet controller, up to 4 timer/counters, 2 UARTs, 4 I/O ports, and more."
Depending on the configuration, the designer can choose from options such as compare/capture, watchdog, master/slave I2C Bus controller, quad SPI, a fixed-point coprocessor, or a floating-point coprocessor.
The Dhrystone 2.1 benchmark score for the DP8051 shows speed improvement from 11.46 to 15.55 over an Intel 80C51 running at the same frequency. The same C compiler with the same settings was used for benchmarking the core vs. the 80C51. This performance can be also utilized as a great advantage in low-power applications, because the DP8051 core can be clocked over ten times slower than the original implementation without any performance degradation.
The DP8051, like all other DCD's 8051 IP Cores, has a built-in support for DCD's DoCD Hardware Debugger, which provides debugging capability for the whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCD provides non-intrusive debugging of a running application. It can also efficiently save designer’s time thanks to a hardware trace feature called the Instructions Smart Trace (IST) buffer. The DoCD-IST captures instructions in a smart and non-intrusive way – it doesn’t capture the addresses of all executed instructions, but only those related to the start of tracing, conditional jumps, and interrupts. This method not only saves time, but also allows the user to reduce the size of the IST buffer and/or extend the trace history. Captured instructions are read back by the DoCD-debug software, analyzed, and then presented to the user as assembly code and related C lines.
DoCD’s Instruction Smart Trace (IST) buffer
to see a larger, more detailed version of this image)The DP8051 family overview
to see a larger, more detailed version of this image)
- Software is 100% compatible with the industry standard 8051
- Pipelined RISC architecture runs 15.55 times faster than the original 80C51 at the same frequency
- Up to 14.632 VAX MIPS at 100MHz
- 24 times faster multiplication
- 12 times faster division
- Up to 256 bytes of internal (on-chip) data memory
- Up to 64 kB of internal (on-chip) or external (off-chip) program memory
- Up to 8MB linear code space (in 80390 mode)
- Up to 16 MB of external (off-chip) data memory
- User programmable program memory wait states
- User programmable external data memory wait states
- De-multiplexed address/data bus allows easy memory connection
- Interface for additional special function registers
- Fully synthesizable
- Static synchronous design
- Positive-edge clocking and no internal tri-states
- Scan test ready
for more information about the DP8051 (Click Here
to see a video), and Click Here
for more details about DCD's on Chip Debugger.
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