Based on their IP Core architecture improvement experiences since 1999, the folks at Digital Core Design (DCD) have introduced two options for the well-known D68HC11:
- Standard: Preconfigured MCU whose configuration is identical to the original HC11.
- Optimized: An individual configuration with extra peripherals and additional custom blocks as required by the application (there’s no need to waste time and money for unused features and wasted silicon).
What does this mean in real life/real design? "DCD’s D68HC11 IP Core family is based on 3 major options: E, F, and K,"
explains Jacek Hanke, CEO at Digital Core Design. "These options are devoted to the specific original MCU, but -- in contrast to it – every single one of them adds an extra value to the design, which means it already has integrated on-chip major peripheral functions."
An asynchronous serial communication interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. A memory expansion unit (with six address ex-tension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB.
Moreover, self-monitoring, on-chip circuitry is included, which protects the D68HC11E against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP – are available to conserve addition-al power. "These modes make the D68HC11 IP Cores especially attractive for automotive and bat-tery-driven applications," adds Hanke.
The D68HC11 IP Core, can be also equipped with an ADC Controller. This allows the use of an external ADC controller with standard ADC software. This extra design feature in DCD’s implementation makes external ADCs visible in the same way as internal ADC's in the original 68HC11E Microcontrollers.
And, last but not least, in order to make the D68HC11 even more adjustable, it’s been equipped with a built-in, real-time, on-chip hardware debugger, allowing easy software debugging and validation. Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running applica-tion. It can halt, run, step into, or skip an instruction, and read/write any contents of the microcon-troller, including all registers and SFRs, and also user-defined peripherals and data and program memories.
DCD’s IP Core comprises also fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.Click Here
for more information about the D68HC11; Click Here
to see a video on YouTube; and Click Here
for more details about DCD’s on-chip Debugger.Key features:
- Cycle compatible with the original implementation
- Software compatible with th e68HC11 industry standard
- I/O Wrapper making it a pin-compatible core
- SFR registers remapped to any 4KB memory page
- Two power saving modes: STOP and WAIT
- Fully synthesizable
- Static synchronous design
- No internal tri-states
- Scan test ready
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