I just had a briefing about Altera's forthcoming Generation 10 FPGAs and SoCs. My immediate reaction was "Ah Ha! Now it all makes sense!"
So, why was I confused in the first place? Well, way back in the mists of time we used to call September 2012, Altera made a big announcement about its next generation devices, saying that these were to be implemented using TSMC's 20nm technology node (see Altera unveils innovations at the 20nm node and "Under the hood" of Altera's 20nm offerings).
No problems so far… but then, in February 2013, Altera announced that it had entered into an agreement for the future manufacture of Altera FPGAs on Intel’s 14 nm tri-gate transistor technology (see Altera's future high-performance FPGAs to use Intel’s 14nm tri-gate technology). As I commented at that time: "I may be wrong, but I think this is the first time an FPGA company has announced a "next-next-generation" technology before their "next-generation" technology has hit the streets. We truly do live in exciting times!"
Well, as I said, all is now clear, because the folks at Altera have just announced their plans for their forthcoming Generation 10 FPGAs and SoCs. In a nutshell:
Delivering the unimaginable with Stratix 10 FPGAs and SoCs
- Stratix 10 FPGAs and SoCs will leverage Intel’s 14nm Tri-Gate process and an enhanced architecture to deliver core performance two times higher than current high-end FPGAs, while enabling up to 70 percent power savings.
- Arria 10 FPGAs and SoCs will be implemented using TSMC's 20nm process and will reinvent the programmable technology midrange by simultaneously surpassing high-end FPGAs in performance while delivering 40 percent lower power than today’s midrange devices.
Stratix 10 FPGAs and SoCs
are designed to enable the most advanced, highest performance applications in the communications, military, broadcast and compute and storage markets, while slashing system power. Leveraging Intel’s 14 nm Tri-Gate process and an enhanced high-performance architecture, Stratix 10 FPGAs and SoCs have an operating frequency over one gigahertz, 2X the core performance of current high-end 28 nm FPGAs. For high-performance systems that have the most strict power budgets, Stratix 10 devices allow customers to achieve up to a 70 percent reduction in power consumption at performance levels equivalent to the previous generation.
Good grief – a 1GHz FPGA – I never thought I'd see the day (excluding esoteric non-mainstream architectures). And we should note that this 1GHz refers to the programmable fabric and on-chip DSP functions and RAMs and suchlike. Altera haven’t told me the speed of the dual ARM Cortex-A9 processor in their Stratix 10 SoC devices, but it will be a minimum of 1.5GHz based on the Arria 10 announcement (see below).
Altera is announcing the technology details of Stratix 10 FPGAs and SoCs today as part of the Generation 10 portfolio introduction, and will disclose more details on the product at a later date. Stratix 10 FPGAs and SoCs provide the industry’s highest performance and highest levels of system integration, including:
- More than four million logic elements (LEs) on a single die
- 56-Gbps transceivers
- More than 10-TeraFLOPs single-precision digital signal processing
- A third-generation ultra-high-performance processor system
- Multi-die 3D solutions capable of integrating SRAM, DRAM and ASICs
All of this leads me to what I think is one of the most intuitive graphics I've ever seen for this sort of thing. I can’t tell you how many times I've heard "Provides xx% performance increase and yy% power reduction,"
only to discover that the two are mutually exclusive. Well, consider the following graphic comparing Stratix 10 devices to their Stratix V forebears:
What this tells us is that – for the same size device (in terms of functionality / capacity) – if we keep the same performance, then we will consume only 30% of the power (green). Alternatively, if we opt to consume the same amount of power, then we will see 40 to 60% increase in performance (blue). Or if we decide we need the maximum performance (2X that of a Stratix V), then we will consume 30% more power (orange). Well, color me impressed (no pun intended).Reinventing the midrange with Arria 10 FPGAs and SoCsArria 10 FPGAs and SoCs
will be the first device families to roll out as part of the Generation 10 portfolio. The device family sets a new bar for midrange programmable devices, delivering both the performance and capabilities of current high-end FPGAs at the lowest midrange power. Leveraging an enhanced architecture that is optimized for TSMC’s 20 nm process, Arria 10 FPGAs and SoCs deliver higher performance at up to 40 percent lower power compared to the previous device family.
Arria 10 devices offer more features and capabilities than today’s current high-end FPGAs, at 15 percent higher performance. Reflecting the trend toward silicon convergence, Arria 10 FPGAs and SoCs offer the highest degree of system integration available in midrange devices, including 1.15 million LEs, integrated hard intellectual property and a second-generation processor system that features a 1.5 GHz dual-core ARM Cortex-A9 processor. Arria 10 FPGAs and SoCs also provide 4X greater bandwidth compared to the current generation, including 28-Gbps transceivers, and 3X higher system performance, including 2666 Mbps DDR4 support and up to 15-Gbps Hybrid Memory Cube support.Stop!
Did you note the fact that the on-chip dual ARM Cortex-A9 processor subsystem in the SoC devices will be running at 1.5GHz
? And this is in the so-called midrange devices, which is why I'm eager to hear more about the processor subsystem in the Stratix 10 SoC devices as discussed above. All of which leads us nicely to the following graphic:
Although simple, to me the above graphic is one of the most startling I remember. When an FPGA vendor announces a new generation of devices, the new midrange devices will obviously "trump" the previous generation of midrange devices, but their performance cannot be so high as to encroach into the realm of the high-end devices implemented at the same technology node.
So, the fact that Altera is implementing its next-generation high-end devices using a different technology node (Intel’s 14nm Tri-Gate process), which provides such a large performance boost, means that Altera feels free to make its next-generation midrange devices out-perform its current generation high-end devices (if you see what I mean).
The key takeaway from the above graphic is that Arria 10 midrange devices will consume 40% less power than their Arria V predecessors while offering 15% greater performance than the current Stratix V high-end devices. My mind is truly boggled! Development suite delivers breakthrough productivity to Generation 10
Generation 10 devices are supported by Altera’s Quartus II development software and tools for higher level design flows that include a software development kit for OpenCL, a SoC Embedded Design Suite and DSP Builder tool.
This leading-edge development tool suite enables design teams to maximize productivity while making it easier for new design teams to adopt Generation 10 FPGAs and SoCs in their next-generation systems. The Quartus II software will continue to deliver the industry’s fastest compile times by providing Generation 10 FPGAs and SoCs an 8X improvement in compile times versus the previous generation. The substantial reduction in compile times is the result of leading-edge software algorithms that take advantage of modern multi-core computing technologies. Availability
Early access customers are currently using the Quartus II software for development of Arria 10 FPGA and SoCs. Initial samples of Arria 10 devices will be available in early 2014. Altera will have 14 nm Stratix 10 FPGA test chips in 2013 and Quartus II software support for Stratix 10 FPGAs and SoCs in 2014. Click Here
for more information or contact your local Altera sales representative.
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