A physical library contains all of the IP elements required to implement a complete SoC, including SRAM compilers, register files, ROMs, built in memory test and repair and standard cells, datapath libraries, power optimization kits, all with options for overdrive/low voltage PVTs, and multi-channel cells. It is used for implementing all IP blocks on an SoC, including processor cores. In the past, a different library may have been used for each area of a chip, with one library optimized for the CPU, another for logic or DSP functions. SoCs typically have multiple, different processors to manage a range of functions (i.e. CPUs, GPUs, DSPs). Each has to be optimized for performance, power or area – or a balance of the three depending on the application. Now Synopsys believes that they have been able to define a single library that can be used across all of these functions. Synopsys DesignWare High Performance Core (HPC) design kit is an add on package that offers an enhanced set of logic libraries, optimized memory instances and methodology documentation and reference scripts to enable designers to improve the quality-of-results in performance, power and area, when hardening their CPU, GPU and DSP cores. By including all of the physical IP elements needs for all processors in a single package, Synopsys believes it will help designers reduce development cost and speed implementation schedules.
I asked Ken Brock, Sr. Product Marketing Manager, Logic Libraries, why this had not been done in the past. He said that it had technically been possible in the past but people wanted to optimize their cores and were using certain libraries to do that. Rather than coming up with a set for each core we wanted to put it all into a single box because most companies use CPU and GPUS in the same chip these days. Even each of these cores may have different needs for certain functions. Battery life is dominated by these components and you have to get the right Power, Performance and Area (PPA) for each of them.
The library is specialized for each fabrication technology. This release is associated with the TSMC 28nm HPM (high performance mobile) process. However, they are also seeing this used in the “green” server and communications market.
Synopsys has already seen some results from the usage of this library and typically a user could see a 10% increase in performance or a 10% area reduction, or a 25% reduction in power, or a 30% reduction in turnaround time. In one example, Imagination saw a 10% area improvement, a 20% drop in leakage power and a 25% reduction in dynamic power. One of the new capabilities that led to this improvement was their specialty flip-flops. These can achieve gains by providing optimal clocking schemes that understand that these flops form part of a larger entity or by manipulating the timing between flops so that critical logic can be squeezed in using a slightly delayed clock.
It appears to me that this is perhaps another step towards logic synthesis becoming more physically-aware in that the library can now be “functionally aware” and the two can play together to bring about more optimizations.Brian Bailey
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