SAN JOSE, Calif. — Xilinx claims it has taped out the first merchant chip in a 20nm planar process at TSMC, its first to use a new FPGA architecture. Samples will be available in the fourth quarter for the chips that Xilinx estimates could boost system performance 50 to 100 percent over those with today's 28nm parts.
The news comes less than a month after archrival Altera announced it will sample versions of its high-end Stratix chips made in Intel's 14nm process using FinFETs early next year. The company also expects to sample mid-range Arria chips made in TSMC's 20nm process at that time.
"TSMC confirmed we are the first with a merchant chip to tape out on its 20nm process," said Dave Myron, senior director of FPGA product management and marketing.
In June, Xilinx announced it worked with TSMC to accelerate plans for FPGAs made in its 16nm process with FinFETs. Those chips will sample sometime in 2014, Myron said.
The 20nm process is the first to use double patterning, requiring a second pass through lithography machine for some critical layers. That will add time and cost to the designs, but Xilinx declined to give specific figures.
To counter the rising complexity, the FPGAs will sport a so-called Ultrascale architecture geared to deliver higher performance. It uses new routing techniques to reduce on-chip congestion and an ASIC-like clocking approach that should allow for more flexible clock placement with less skew.
Ultrascale also sports enhanced critical paths for key on-chip blocks. Xilinx will use the architecture for its follow on products made with 16nm FinFETs and beyond. Xilinx said high-end Virtex versions of the chips will power 4 x 100 Gbit/s switches and bridges; mid-tier Kintex versions will appear in 256-channel ultrasound and vision processing systems.
The 20nm process will boost performance about 66 percent for 2.5-D chips that place multiple dies on a substrate. Data rates between dies should rise from 1-2 Tbit/s today to 3-6 Tbits/s, or about the speed of an on-die link, Myron said. In addition, Xilinx expects, at 20nm, to double the number of connections between dies on 2.5-D chips to about 20,000.