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Micron Sampling 16nm NAND

7/16/2013 09:10 AM EDT
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Peter Clarke
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Blowing past Toshiba/SanDisk
Peter Clarke   7/16/2013 9:37:15 AM
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Given that Toshiba/SanDisk's 1Y generation stayed at 19-nm

http://www.eetimes.com/document.asp?doc_id=1280886

This looks likes a win for Intel/Micron planar HKMG memory cell structure.

But of course the proof is in the system-level pudding.

 

Does this put clear water between Micron and its competitors?

mcgrathdylan
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Re: Blowing past Toshiba/SanDisk
mcgrathdylan   7/16/2013 1:50:40 PM
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Glen Hawk emphasized the fact that this part is the smallest die size 128Gb NAND available much more than the 16nm process technology. But I agree that given the surprising move by SanDisk/Toshiba to stay at 19nm, Micron's migration down to 16 is impressive and differentiating.

Peter Clarke
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Re: Blowing past Toshiba/SanDisk
Peter Clarke   7/16/2013 2:12:36 PM
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Lets see what Samsung and Hynix can do?

goafrit
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Re: Blowing past Toshiba/SanDisk
goafrit   7/17/2013 10:48:09 AM
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Samsung generally does not move first in some of these new areas. They wait for someone to do all the hard works and then with their cash pile jump in and take over the market with volume and great pricing. Micro is a great company but NAND business may be very challenging now

double-o-nothing
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Re: Blowing past Toshiba/SanDisk
double-o-nothing   8/18/2013 10:27:16 AM
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goafrit
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Re: Blowing past Toshiba/SanDisk
goafrit   7/17/2013 10:46:19 AM
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Is the innovation in feature size or crafting better circuit architectures? 16nm can help pack more memory in small space which is good but sooner or later we just have to redesign the foundation of transistor to make real progress. After 16nm, maybe 11nm and then we are cut-off with quantum mechanical effects to go lower.

Peter Clarke
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Re: Blowing past Toshiba/SanDisk
Peter Clarke   7/17/2013 10:50:47 AM
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The introduction of a flattened planar memory cell at 20-nm by Intel-Micron seems to be standing the companies in good stead for this move to 16-nm. Interested whether it also represents a lead over Samsung and Hynix.

 

These companies usually tend to compete hard even with engineering ennouncements

goafrit
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Re: Blowing past Toshiba/SanDisk
goafrit   7/17/2013 11:09:53 AM
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>> Interested whether it also represents a lead over Samsung and Hynix.

Samsung does not seem to lead in any of these innovations. Yet, they find ways to catch up and redesign any industry. The move to lower feature size is excellent but over time, that will not be a major advantage. Anyone that figures out will be the long-term leader.

Tom Mariner
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Not that long ago
Tom Mariner   7/16/2013 2:13:44 PM
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Thanks guys for making me feel old! It seems like not that long ago that I was in the Boise Micron plant watching the boats of wafers float overhead and hearing the brags of the engineers that they were "sub micron".

But I am that old -- I can remember us repairing mask or design defects so we could test by "smushing" traces together or apart with a probe needle viewed through an optical microscope.

Tom Murphy
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Re: Not that long ago
Tom Murphy   7/16/2013 4:45:23 PM
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Tom Mariner:  You're not along, my friend.  I remember those days all too well.  I even remember when we talked about sub-micron as a futuristic goal!

franzChen
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Impressive
franzChen   7/16/2013 2:49:09 PM
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It's by QP? How is the die size compared to Samsung's TLC 128Gb NAND?

resistion
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lowest cost?
resistion   7/16/2013 7:04:36 PM
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With quadruple patterning? Figure they need to approach 10 nm to be more cost-effective.

mcgrathdylan
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Re: lowest cost?
mcgrathdylan   7/16/2013 8:20:24 PM
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@resistion- do you think they had to use quadruple patterning to make this part? I have not had any indication that that is the case. I can look into it.

resistion
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Re: lowest cost?
resistion   7/16/2013 9:33:34 PM
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It's pitch quartering by sidewall spacer processing, not four exposures. SK Hynix showed it as well at IEDM 2011.

elctrnx_lyf
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Re: lowest cost?
elctrnx_lyf   7/17/2013 6:30:24 AM
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Hopefully the SSD's will become much cheaper in the future.

resistion
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Re: lowest cost?
resistion   7/17/2013 10:28:47 AM
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This process should be good down to 9-10 nm. Would transistors even work that small?

Peter Clarke
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Re: lowest cost?
Peter Clarke   7/17/2013 10:46:50 AM
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Well Intel has indicated that they  believe 10-nm is the last node for planar NAND flash memory  but they will engineer 3D-NAND with a 40-nm minimum geometry in parallel with the 16-nm NAND generation.

 

We will see

resistion
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Re: lowest cost?
resistion   7/17/2013 10:59:26 AM
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If it were easy and not cost-increasing to process 32, 64 or more layers of cells, they could have done the 3D NAND at even larger, more mature geometries, like 65 nm or 90 nm.

mhrackin
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How about other trade-offs?
mhrackin   7/17/2013 12:06:00 PM
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I'm curious as to what other performance parameters are impacted by this.  The specifics important to me relate to data reliablility and retention.  How many R/E/W cycles at the individual cell level?  Operating temperature range?  Noise margins?  The list goes on....  I know the transition to MLC required substantial improvements in the SW/controller algorithms to deal with these.  I suspect far too many users (and even design engineers) aren't aware of these limitations, and the consequences (e.g. even USB memory sticks wear out eventually and shrink in capacity during their service life, and the same is true of SSDs).

mcgrathdylan
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Re: How about other trade-offs?
mcgrathdylan   7/17/2013 8:17:42 PM
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Good questions. I wasn't aware that SSDs and memory sticks shrink in capacity. That's not something you hear a lot about. Would you agree that the tradeoffs are worthwhile?

any1
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Re: How about other trade-offs?
any1   7/18/2013 9:07:39 AM
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I think that many of us are aware that NAND flash chips "wear out" over many read/write cycles.  And so companies employ various software algorithms to try to mitigate the physics of NAND device break down.  In some cases that means "bad" cells are excluded and not used hence the usable memory capacity is lower.

mhrackin
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Re: How about other trade-offs?
mhrackin   7/18/2013 10:46:53 AM
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I'm very familiar with the various countermeasures for dealing with the raw NAND flash limitations.  My preference as a systems architect is using integrated systems from suppliers who are major players in the IP arena of these algorithms; there are only a handful of companies that control the vast bulk of that IP, and most have partnerships with the others cross-licensing the IP.  Regardless, none of these are bullet-proof, and each innovation in NAND flash density requires another layer or two of protection.  Although the details of this latest die-shrink are not disclosed, I would imagine that it entails both geometry shrink AND level-splitting the MLC structure.  That combination will require a major increase in the controller complexity to maintain the same level of data and device reliability. IMO, even the present level of that reliability is marginal for highly-sensitive applications (think medical devices, secure servers, etc.).  Too many people view this technology as the "magic bullet" that side-steps all the limitations of electro-mechanical (HDD), not realizing that even these have to be used in redundant schemes (e.g. RAID or equivalent) to get the level of system availability needed.

resistion
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16 nm MLC = 19 nm TLC = 11 nm SLC
resistion   7/19/2013 10:03:50 PM
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Not sure about TLC status, but if Samsung had 18 nm TLC they could be ahead of everyone. However the truly intrepid can march toward 11 nm and beyond.

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