LONDON – Startup company SuVolta Inc. has announced that it is working with Taiwanese foundry United Microelectronics Corp. (UMC) on a 28-nm low-power manufacturing process aimed at mobile applications.
SuVolta has also said it has manufactured a Cortex-M0 processor core from ARM in 65 nm bulk planar CMOS, which has benchmarked the low power possibilities of SuVolta's Deeply Depleted Channel (DDC) technology.
The DDC technology uses doping techniques to create a ground plane under a transistor and represents an alternative way to build low power logic transistors to the fully-depleted silicon-on-insulator (FDSOI) and FinFET processes that are currently being deployed across the industry. The SuVolta method appears to achieve similar results to the FDSOI approach, but avoids the cost premium of starting with SOI wafers. The FinFET method of etching back the surface silicon to leave fins as the sites for transistors, pioneered by Intel and being adopted by TSMC, Samsung, and Globalfoundies, is the most extensively researched approach.
In presentation materials, SuVolta, a fabless company, said that it now has six DDC deployment programs in place with top-tier semiconductor manufacturers ranging from 65 nm down to 20 nm manufacturing processes. SuVolta did some of its early development work with Fujitsu Semiconductor Ltd., and was also thought to be working with Globalfoundries Inc. (See: Globalfoundries mulls third manufacturing option.)
SuVolta sees a large market opportunity not only in mobile application processors, but also where it can reduce memory power consumption in areas such as DRAM, imaging, and microcontrollers.
Comparison of PowerShrink low-power design and planar CMOS at 65nm. Source: SuVolta.
SuVolta said that when compared to an identical ARM Cortex-M0 processor in a conventional 65-nm CMOS process with a 1.2-V supply voltage, an implementation using DDC transistors operated at 0.9-V with a benefit that could be measured in various ways. These included: 50 percent lower power consumption at the same 350MHz clock frequency; 35 percent higher clock frequency at the same power consumption; or 55 percent higher clock frequency at matched supply voltage.
Noel Hurley, vice president of strategy and marketing for the processor division at ARM, said a press release issued by SuVolta:
ARM’s heritage is based on low power, so technologies that can further improve power consumption, such as DDC technology from SuVolta, will always be welcomed by ARM and our partners. SuVolta has shown that the DDC technology, when incorporated into an ARM processor, can provide additional power reductions or a significant performance boost. As the Internet of Things continues to expand, innovative ultra-low power technology for sensors and other devices will be vital to ensure that ARM remains at the forefront of this opportunity.
UMC is working on two versions of the DDC technology. One is a complete "PowerShrink" platform where in all transistors are made using the DDC process. This will provide the ultimate power and performance benefit, SuVolta said. The second approach SuVolta calls DesignBoost, and involves swapping out particular transistors where there is a need to reduce leakage or lower the minimum operating voltage. The DesignBoost approach has the advantage that in the design phase it can be applied to existing design databases where a subset of transistors is replaced with DDC transistors.
"In the next weeks and months we expect to see promising results from joint technology development with SuVolta to further validate the power and performance benefits of the DDC technology in UMC's 28nm HKMG process," said T.R. Yew, vice president of the advanced technology division at UMC, in the same statement.
Jeff Lewis, senior vice president of marketing and business development at SuVolta, said that he expected to development process and integration of DCC with UMC's 28-nm HKMG process could take another year with the creation of an ARM-based test chip in the process as part of the collaboration. This would make the process available for third party design in 2014 and likely producing silicon in 2015.
SuVolta distributed statements endorsing its DDC technology attributed to several analysts.
Rich Wawrzyniak, a market analyst with Semico Research Corp., said the SuVolta technology reduces both active and standby power while increasing performance while using planar CMOS transistors and bulk CMOS processes. He did not say what the reduction was compared against but it should be presumed it is against conventional CMOS bulk process at the same geometry.
"By providing a mid-life kicker, the DDC technology can enable companies to get the benefits of scaling to a smaller node without incurring the significant and increasing design costs associated with the shrink, or migrating to new process technologies like 3D or FDSOI," said Len Jelinek, chief analyst at IHS.
"One key advantage of SuVolta is the ability to use the process flows that already exist within the high-volume wafer manufacturing facilities, which can increase the lifetime of capital-intensive wafer fabrication facilities," said Handel Jones, CEO International Business Strategies.
SuVolta also announced that it has recruited Louis Parrillo as chief operating officer and that he will lead the effort to integrate the DDC technology with SuVolta's several partners. Parillo has held executive positions at Unity Semiconductor, Freescale, Spansion, and Motorola.
A technical paper appeared in Micro Magazine in February 2013 on how to use DDC technology to reduce transistor variability within an IC and thereby achieve higher performance at lower power, again it is presumed to be compared against conventional bulk planar CMOS (see Reducing transistor variability for higher performance, lower power chips.