mlloyd - A few years back we decided to stay away from the high speed SERDES and use a source synchronous LVDS interface instead. This way we could attach to low cost as well as high end FPGAs. The interface does use a fair amount of pins (8 data lanes) but can provide up to 16Gb/s total bandwidth with a 500MHz clock. This turned out to be a good choice because the low cost zynq 7010 and 7020 don't currently support high speed serdes.
Congratulations, Andreas, on shipping your product and nearing your large milestones. I am curious about your eLink interface between the Zynq and Epiphany. Since you designed the Epiphany from scratch, is it able to make use of the high-speed transceivers offered by the Zynq? We commonly interface processors to FPGAs in my business, and it is always a challenge to find processors that have high-speed buses that we can use to communicate with our FPGAs.
The Parallella actually has a ~10Gb/s memory mapped low-latency link (through the "PEC" connector) that can be used to to construct some interesting large scale topologies. See the specs here.http://www.parallella.org/board
Dylan- Thanks! Shipping 6,300 boards is the one that really matters to us. The expectations of 5,000 KS backers has been a big weight to carry for 9 months now. Fortunately for us they have been incredibly patient and understanding. We'll definitely keep you posted. If you don't hear from us something i wrong:-)