How fast can you bring up design prototypes and get them into manufacturing?
Earlier this month, Asset InterTech merged with Arium, a supplier of software debug and trace tools for Intel and ARM-based designs. Together, the companies hope to help system designers accelerate prototype testing.
This week, I spoke with Glenn Woppman, president and CEO of Asset. The acquisition is all part of Asset's strategy to provide greater visibility into designs that no longer have the test ports that used to yield so much information in the past. Asset, a big proponent of built-in self-test (BIST), is willing to creatively use all of the available hooks into a chip to get as much insight into what is happening on it during the verification process as possible.
Traditionally, Asset was focused on boundary scan and the needs of test engineers. Then, as physical access went away, the company moved to microprocessors for test and then BIST as buses went from parallel to serial (PCIe, SATA, etc.) above 5 Gbit/s.
"The bottom line is, visibility and test points are going away," says Woppman, "either due to packaging or high-speed bus issues." For instance, signal integrity validation can no longer be done via probe, and test points add capacitance, so external instruments cannot see what the silicon sees.
Whereas Asset's focus has traditionally been on the hardware engineer, Arium has remained focused on the embedded software engineer's needs. "Now we are bringing the two together to support IP and silicon," says Woppman, "Giving engineers more visibility as functional bit speed continues to increase."
Debugging is proving more difficult. Designers are dealing with software and IP from multiple vendors and design teams, and it has to come together and be tested. Combine this with trends in packaging technology, which are leading to more integrated products with fewer I/Os.
"Now we have the tools, technology, and talent to help system guys as they are adopting all of these new technologies, allow them to get their boards tested, validated, and debugged so they can move to manufacturing test."
Take, for example, the Intel Silicon View Technology (Intel SVT), which is a set of capabilities embedded in Intel processors and chipsets that works with platform debug, electrical validation, and board manufacturing test solutions available from Intel and third-party solution providers.
Woppman notes that now Asset has ScanWorks products that address all parts of the validation. For instance, for platform debug there is ScanWorks Arium; for electrical validation there is ScanWorks HSIO; and for manufacturing test there is ScanWorks BST and PCT. "We are the only company supporting all three of these areas."
For Asset, the goal is to enable the experts who need to develop the tests for software/firmware/memory debug and test. Then, allow the design engineer to bring up the project and hit a button that runs the test and shows the results. Then, the design engineer can focus on overall performance rather than board assembly.
Just out of the gate, Asset has essentially rebranded the Arium product with the Asset InterTech ScanWorks brand name. So, how long until the product lines are truly integrated? Woppman tells me that Asset could look first, probably within a year, into common hardware, and he expects its first actual "major integration project" to be about a year out (there are already smaller ones underway). His idea is that the company will move toward some common hardware that all of the applications run on, which will lower the cost for the customer.
I had one more question for Woppman, and it is one that's on everyone's mind, I think, when a merger takes place. What about the jobs? He says all of the people who worked for Arium were offered employment, and all accepted. He points out that there is no real duplication.
"We have been working together for awhile as two private companies. It's really going well, and both teams are excited," says Woppman. The former CEO of Arium, Larry Traylor, is now VP of software development at Asset.