Oasys Design Systems Inc., a vendor of RTL synthesis tools, has raised a round of funding led by Intel Capital, Xilinx, and Joe Costello, former CEO of Cadence Design Systems Inc. The company disclosed the news on its website.
Joe Costello, CEO of Orb Networks, has a seat on the board of directors of Oasys.
As with previous rounds, Oasys has not revealed how much money it will receive. The company said the funds would be used to expand sales, marketing, and product development.
The latest round comes 15 months after a Series B round led by Intel Capital and Xilinx. The money from that round was earmarked at the time for spending on R&D and expansion of support.
Oasys, which was founded in 2004, claims that its RealTime Designer software enables the register-transfer-level synthesis of 100 million gate designs and reduces or eliminates design-closure iterations between synthesis and layout. Previously Oasys had announced a number of high-profile customer wins, including Texas Instruments, Qualcomm, and Xilinx.