With the exception of processors, IP blocks used to be small, isolated functions. Not so these days: The size and complexity of IP blocks are growing to the point where they are now subsystems that look very similar to things that would have been whole chips just a few generations ago.
Synopsys has just released the second of their sub-system IP blocks: A sensor hub. The first was an audio sub-system.
Sensors are a fundamental part of the Internet of Things. This sector often requires the combination of multiple sensors, analog conditioning circuitry, digital intelligence, and wireless communications, while also needing to be small, low cost, and low power. Often, they will have to operate on the power they can scavenge from their environment. When power is that important, you can't get to a low-power solution just by a few optimization techniques, you have to look at the overall architecture.
Indeed, architecture plays an important part of any optimized system, and that is the core tenet that Synopsys has built into their sensor hub IP block. Instead of utilizing a typical bus-based architecture to enable the processor to handle data processing and sensor access, Synopsys has brought all of this into the core, and it can treat many of these things as if they were registers rather than memory. They are not part of main memory, but local embedded SRAM that does not have to contend with other clients. That is the benefit that comes from having your own processor that can be fine-tuned for this kind of application -- in this case, the ARC processor.
Synopsys digital sensor hub with ARC processor and accelerators, Source: Synopsys.
The IP block is purely digital and does not contain any of the many possible sensors because they tend to be very process specific and analog in nature. The IP subsystem is the digital logic necessary to coordinate all of the functions that you may wish to do with those sensors and to send that information to the rest of the chip via a standard bus interface. This gets to the heart of the system. It is not a predefined solution, it is a set of software and hardware accelerators that can be selected based on the power and performance required.
Let's take a look at one example: A square root function is often used to determine the orientation of a device and when it should switch the display.
Three options for display rotation calculation.
In the table, three solutions are shown. The first is a software-only implementation of the function and it shows the amount of code space required and the time it takes to complete the function. In the middle column, a full hardware acceleration solution is selected in the GUI that comes along with the subsystem. The code space and time to complete the function are now much reduced. But a hybrid solution can also be defined where a tradeoff is made between the area and time. I asked why power is not treated in the same way and was told by Rich Collins, product marketing manager, IP subsystems, that the generator operates fast enough that this can be assessed in other tools in the flow.
The subsystem will be available in October for early partners. Evaluations are underway now. At the moment, they are working with partners, including Xsens, a 3D motion tracking technology with a focus on aerospace and industrial markets.