There seems still some way to go in terms of nm transistor size, and already we are expanding into 3 dimensions. Have the esperts taken this into account? My feeling is the 3D expansion will carry us a fair bit further. Could someone who knows more than I do (which is not much) comment?
Was n't it you yourself who reported a couple of weeks back on Samsung's 3D NAND -- stacked one cell on top of another on a single wafer ?
With time, such 3D technology will spread into processors and memory - processor combos as well. Though the cost per transistor may increase in such stacked devices due to cost of addition of isolation & vertical interconnects etc., the cost per system & power consumption would go down radically due to electrical reasons. How is that for not having to wait for adequate throughput from EUV but still stay on the growth path ?
Balanced, comprehensive and well-reasoned coverage is what we will keep depending on you for.
@ Garcia - Lasheras : selective presentation of data ( graph showing saturation of clock rate ) only damages one's own credibility. As it should have been clear to you this is a Technical Forum and participants are well aware of clock - rate vs multi - processor arguments as options to deliver a certain GFlops. That train has long left the station.
@chipmonk0: "selective presentation of data ( graph showing saturation of clock rate ) only damages one's own credibility".
Thak you very much for your value judgement...
"As it should have been clear to you this is a Technical Forum and participants are well aware of clock - rate vs multi - processor arguments as options to deliver a certain GFlops"
I'm pretty aware of this, but not everybody share the same skills or knowledge. The graph is included in a blog that I wrote for the All Programmable Planet community, in which I tried to give a very simple physical explanation about why clock rates doesn't fit with Moore's law beyond a process limit despite the fact that transistor number does. If you are really interested, here you have the full history.
The "selective presentation of data" I expose was obtained & kindly shared by Dr. Colin Gillespie, from the Univerity of Newcastle -- UK. In his original blog, he explains how he collected and analyzed the raw data -- you can check it in deeper way if you want to.
"That train has long left the station"
I started working in the clock related problems in CMOS processes in year 2001.
From your comments, I deduce you are pretty interested in the Moore's Law demise or survival topic. I plan to be in the related EETimes week in review chat tomorrow... maybe shall I see you there?
Indeed the economic stop seems to be a far more predicatable one than the technological stop. Not only will very few players be able to afford to build a fab or even tape out an IC in 7 nm or 5 nm or whatever the last CMOS node is, but it is also likely that very few ICs will command the enormous volumes required to justify the expense of developing them and getting them released to production.
@rick merritt >> Regarding graphene (along with many other nano-particles) and toxicity at the human cell-level has been raised in the past few months (please google it and you may find the topic interesting). I also have issues with the "fact" that the only byproduct of hydrogen fuel cells is supposed to be water. Donald Rumsfeld 'poetry' regarding the Knowns and the Unknowns may hold true here (please google it and you may find that interesting also). Cheers