How times change. I was chatting with someone recently about the first single-board computer he owned back in the late 1970s. My friend was reminiscing about doubling his SRAM capacity from 1KB to 2KB and how large this seemed at the time. Now, of course, we have memory devices and subsystems that boast humongous capacity and incredible performance. The problem is that our requirements for capacity and performance -- coupled with low power consumption -- are outstripping the capabilities of traditional memory architectures.
I'm not an expert in memory technology, but I like to think I know enough to be dangerous. Up until now, DRAM memory ICs presented in DDR3/DDR4 memory modules have offered the optimum tradeoffs among capacity, performance, and power consumption. Though these memory subsystems are incredibly sophisticated, they are not keeping up with today's state-of-the-art application requirements.
I was chatting with the folks from Micron the other day, and they said that, to address the memory issue, they had basically started with a clean slate and said "If we were to have a next-generation universal memory technology, what would it look like?" The answer is the hybrid memory cube (HMC), which involves a chip package containing a 3D stack of DRAM memory die connected using through-silicon vias, as illustrated below.
One problem with current memory architectures is the intensive controller overhead. In an HMC, the control functions are implemented in a special logic layer/die that forms an integral part of the 3D silicon stack. The HMC combines a packet protocol with an abstracted memory interface; this basically means all the complicated control takes place inside the HMC itself. As a result, according to Micron, a single HMC can produce an incredible data bandwidth of 160GBytes/sec. (Multiple HMCs can be chained together to appear as a single, mega-humongous memory, but that's a story for another day.) A single HMC can provide more than 15X the performance of a state-of-the-art DDR3 memory module while consuming 70 percent less power, the company says on its website. Furthermore, the stacked architecture uses almost 90 percent less space than today's RDIMMs.
It's important to note that Micron isn't exploring this technology by itself. The Hybrid Memory Cube Consortium is backed by a bunch of major technology companies, including Altera, ARM, Samsung, and Xilinx.
Speaking of Altera, that company and Micron announced today that they've demonstrated interoperability between Micron's HMCs and Altera's Stratix V FPGAs using a full 16-transceiver HMC link. This will allow users to start experimenting with the new technology as soon as Micron starts officially sampling HMCs this year. Volume production is expected to ramp up in 2014. This ties in nicely with the deployment plans for Altera's Generation 10 devices, which will include Arria 10 FPGAs and SoCs implemented using TSMCs 20nm process, followed by Stratix 10 FPGAs and SoCs, which will be implemented using Intel's 14nm Tri-Gate process.
I cannot wait. Considering the amount of time I spend shouting at my computer for taking so long to do things, it's safe to say that I can use all the memory capacity and bandwidth I can get.