Two researchers have teamed up to launch EDA startup Synflow SAS. The company is based near Rennes in Brittany, France, and already has a product available to license.
That product, the result of several years of academic research by founders Matthieu Wipliez and Nicolas Siret, is Synflow Studio, an Eclipse-based integrated development environment (IDE) for hardware designers. The software requires as its input a proprietary C-like language, C~ (pronounced C-flow), together with graphical representation and manipulation.
C~ is a bit-accurate, cycle-accurate C-based language for hardware description for simulation and synthesis. The company claims it also allows designs to contain parameterized components, such as single-port/dual-port RAM, asynchronous/synchronous FIFOs and so on. The company has already designed a number of circuits with the tool including an Ethernet transceiver, AES cryptographic core and a processor.
On its website the company stresses that Synflow Studio is aimed at hardware engineers and that it allows expression at a higher level of abstraction than the RTL supported by VHDL and Verilog, but that it does not require engineers to write software. Rather than supporting high-level synthesis of arbitrary C/C++ code Synflow aims to support faster design of high-performance hardware, the company states.
Matthieu Wipliez, CTO of Synflow SAS.
"With Synflow Studio, the user designs hardware as a hierarchical network of parallel tasks connected together, just like in hardware, but with a graphical editor. The graphical view is much more appropriate for understanding the structure of a design, and has the advantage that it checks everything is correct at compile time -- all ports are connected, they have compatible data types -- which leads to huge time savings," said Wipliez, CTO of Synflow, in an email to EE Times. The company claims that Synflow Studio and writing in C~ allow engineers to design hardware blocks two to five times faster and to simulate up to 20 times faster than conventional methods.
"From this kind of description [of C~], the tool is capable of: Generating RTL code, both in VHDL and Verilog, that is synthesizable, portable, and readable, as opposed to the spaghetti code that most HLS tools produce," said Wipliez.
He added that these features also allow the tool to simulate a description 10 times faster than at RTL by generating a Java representation. They also allow the export of scripts and wave format for RTL simulators, and for synthesizers to take the code forward for RTL synthesis down to the gate level. "Currently only FPGA tools are supported. Adding support for ASIC tools is planned for a future version," Wipliez added.
Synflow Studio is priced at $100,000 for a multi-seat development team license. Customers can also get a free-of-charge evaluation license for 1 month or a $1,000/month evaluation license for 3 to 6 months. Private individuals who work on open-source projects can also have a free-of-charge license.