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9/16/2013 11:05 AM EDT
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Matthieu Wipliez
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Re: An intermediate level of abstraction?
Matthieu Wipliez   9/17/2013 8:41:26 AM
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Hi Nicolas,

the major difference is that C~ is a programming language dedicated for hardware, contrary to C/C++, which are software languages. Try translating 'malloc' or 'new' to hardware ^^ SystemC is somewhere in the middle, but I think it is not the solution.

C~ is above RTL, as it does not have an explicit clock, reset, or signals. The language is still cycle-accurate, so it's lower level than the code you would typically write with HLS. So it's kind of in-the-middle, we use a model of computation derived from dataflow process networks, which define computations in terms of action firings; in C~ a firing is executed in a cycle.

As I explained in the post I linked to above, extending C++ is probably not a good idea, it is difficult to parse, complicated to analyze, and you still have to deal with the C++ layer (hello ugly error messages).

Matthieu Wipliez
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Re: An intermediate level of abstraction?
Matthieu Wipliez   9/17/2013 9:02:36 AM
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Hi GSMD,

yes I'm aware of Chisel, I included it in my post on Synflow's blog Beyond RTL part 2: Domain-Specific Languages. I think Chisel is a good idea, like MyHDL and similar efforts. It has the advantage of being open-source, but being open or close source, or free or not, does not seem to have made a big difference in EDA historically.

Now back to Chisel, it is a bit like SystemC in that it is based on an existing, large, complex language (Scala is much better than C++, but it is far from being simple). Is the designer really free from having to deal with the Scala layer? Then it's a matter of taste, but I find Chisel's syntax complicated, and its semantics difficult to understand ('when' and 'unless' to do if/then/else but in a slightly different way).

Matthieu Wipliez
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Re: An intermediate level of abstraction?
Matthieu Wipliez   9/17/2013 9:22:00 AM
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Hi Peter,

yes these are big questions, we look forward to customers' reactions! Graphical design is a tough question, too. We already know it's not perfect for every use case in its current form, that said if done well graphical can be awesome. Anyway, it is already a huge improvement over how VHDL/Verilog/SystemC do it!

What we're saying is that software engineers may well get interested in designing hardware, but if they do they should not expect to dump a piece of C and expect the best hardware there is (HLS had promised that, I already blogged about why it will never be able to do that). However, if software engineers do get into hardware design and want a high quality of results, they would definitely go a lot faster with C~ than if they had to use VHDL/Verilog.

AZskibum
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Re:Chisel
AZskibum   9/17/2013 1:21:17 PM
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"And why has HLS not worked?"



Two basic reasons: (1) Hardware designers are reluctanct to move from HDL to C -- even to hardware-friendly SystemC, and (2) The productivity gains of HLS only apply to DSP-oriented designs -- number crunchers. Try designing a complex state machine or a serial comm interface with HLS. Yes, it can be done, but by the time it is done, the designer wonders exactly what the point of that exercise was.

jandecaluwe
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The event-driven paradigm
jandecaluwe   9/17/2013 2:40:20 PM
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Most HDLs that have been proposed are like Chisel and C~: registers are explicit, and events such as clock edges are implicit.

Notable exceptions are Verilog and VHDL. These HDLs follow the event-driven paradigm: registers are implicit and events are explicit.

Would-be HDL language designers seem to ignore this historical lesson systematically. The HDL language winners are the exception, and all those other HDLs are all but forgotten.

Why is that? Because the event-driven paradigm is much more expressive for modeling and better suited to verification (which is much harder than design itself). This is what the market wants and needs, not the focus on "full synthesizability" or "generating hardware".

In addition to SystemC, there is one more exception that I know of: MyHDL. MyHDL proudly follows the event-driven paradigm, like Verilog and VHDL. Of all the newer HDLs that have been proposed, it is the only one afaik.

Jan Decaluwe (the MyHDL guy)

Peter Clarke
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Re: The event-driven paradigm
Peter Clarke   9/18/2013 6:32:39 AM
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Thanks Jan

And MyHDL has the advantage of being open-source.

If that is an advantage????

 

 

 

Peter Clarke
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Re: The event-driven paradigm
Peter Clarke   9/18/2013 6:32:40 AM
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Thanks Jan

And MyHDL has the advantage of being open-source.

If that is an advantage????

 

 

 

jandecaluwe
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Re: The event-driven paradigm
jandecaluwe   9/18/2013 8:05:45 AM
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@Peter said: "And MyHDL has the advantage of being open-source. If that is an advantage????"

I expect people to use MyHDL primarily for technical reasons. Sometimes I don't even mention the open-source aspect.

The MyHDL developers try to make a better HDL in the first place. However, in no way this means throwing everything from Verilog/VHDL away. The event-driven paradigm is what the winning HDLs have in common, and I think it is an extraordinary good and successful concept.

Matthieu Wipliez
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Re: The event-driven paradigm
Matthieu Wipliez   9/18/2013 9:14:05 AM
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Hi Jan,

I'm not sure what you mean by 'registers are implicit [in Verilog/VHDL]'? How are they implicit? In C~ we have state variables, that translate directly to Verilog/VHDL regs/signals. We also have local variables, that are promoted to reg/signal if they are used over more than one cycle.

Additionnally, if you take a look at C~, you'll see that the language is cycle-accurate: what happens at each clock cycle is explicitly defined, just not in terms of 'rising_edge'. Similarly, a task's behavior is expressed with 'while', and 'if', and in the end it is transformed to a FSM with states and transitions.

I don't know about event-driven's suitability for verification, but if it is indeed more appropriate, then I guess we can always translate C~ designs to an event-driven representation (after all that is what we do when we generate VHDL or Verilog). Maybe it depends on the kind of designs you do, in some cases event-driven modeling might be better, in other cases it might not?

jandecaluwe
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Re: The event-driven paradigm
jandecaluwe   9/18/2013 12:36:52 PM
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@Matthieu said "I'm not sure what you mean by 'registers are implicit [in Verilog/VHDL]'? How are they implicit?"

In Verilog/VHDL/MyHDL you don't declare hardware registers. Signals/variables/regs imply hardware registers, or combinatorial logic, or both, strictly by how they are used in the model.

"Additionally, if you take a look at C~, you'll see that the language is cycle-accurate: what happens at each clock cycle is explicitly defined, just not in terms of 'rising_edge'."

In Verilog/VHDL/MyHDL, one can choose to model cycle-accurately (e.g. for RTL-style synthesizable models) or not (e.g. for higher-level models and test benches). This demonstrates how the event-driven paradigm is more powerful, which is especially important for verification.

"I don't know about event-driven's suitability for verification, but if it is indeed more appropriate, then I guess we can always translate C~ designs to an event-driven representation"

In practice, designers want a strong modeling and verification language in which you can also design hardware, not a narrow implementation-oriented design language.

 

 

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