Everyone who attends DesignCon and many engineers who don't know the hazards that high-speed digital signals face as they travel through a circuit board. It's a dangerous place. There's crosstalk, skew, trace width, power-supply fluctuations, interconnect losses, and so on. Any of these conditions can affect jitter, causing a receiver to misinterpret a bit.
Anyone who must analyze jitter probably uses a software tool for the task. Often, engineers use software built into real-time oscilloscopes on measured data. But what about performing jitter analysis on simulated data, before a prototype is ever built?
A paper presented at the 2013 IEEE Workshop on Signal and Power Integrity discusses a method for using an oscilloscope's jitter-analysis software on simulated waveforms, which gave the authors insight into how a high-speed serial link might perform before building it.
The paper's authors developed a method where they simulated a serial link and analyzed it for jitter, then built it and compared simulated jitter to measured jitter. The test board, shown below, consisted of two Altera Stratix II GX FPGAs connected through a 190-mm differential transmission line. It also contained several single-ended 3.3 V signals running at less than 200 MHz. These were the aggressors used to simulate and measure jitter in the serial link that resulted from crosstalk.
A test board for comparing simulated to measured jitter consisted of two FPGAs.
The simulation consisted of modeling the board's physical structure in the area of concern. Next, the authors simulated the serial link and aggressor signals and ran them through jitter-analysis software in an oscilloscope. The test results compared the simulated to measured eye diagrams with the aggressors off and then on. By separating the jitter into its components, the authors could see a dramatic increase in BUJ (bounded uncorrelated jitter) in both the simulated and measured eye diagrams with the aggressor signals turned on.
To get the details of the procedure, including modeling techniques and test results, download the whitepaper "An Innovative Simulation Workflow for Debugging High-Speed Digital Designs Using Jitter Separation" from Agilent Technologies, at DesignCon Community. You must be logged in to download the paper.