Barco Silex has released a multichannel video-over-IP with JPEG 2000 reference design. The reference design integrates its JPEG 2000 Encoder and Decoder IP cores, a memory controller core, along with the SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP cores from Xilinx now available for Xilinx 7 Series FPGAs and Zynq® All Programmable SoC. The design is able to encapsulate and de-encapsulate up to four high-definition streams (1080p60), to optionally compress or decompress those four streams with JPEG 2000, and to transport them over 1 Gbit/s (compressed) or 10 Gbit/s (uncompressed) Ethernet.
Real Intent has released its 2013 version of its Ascent Lint product. Ascent products find errors prior to Verilog or VHDL simulation, leading to improved quality of results (QoR) and higher design team productivity. The new version delivers enhanced support for SystemVerilog, Verilog, and VHDL languages, and improves ease of use in the GUI and low-noise reporting of design issues. A new integrated Emacs-mode feature enables users to view and manage all lint violations at each RTL source location for easier debugging. Users now can edit the source code, manage violations, and rerun Ascent Lint to view updated violations from within the Emacs editor.
Synopsys has released CODE V Optical Design Software, version 10.6. This release delivers a new optimization feature to speed the design of advanced optical systems. In addition, the release provides new charting capabilities and analysis improvements that enable faster, more flexible optical design validation. The new Step Optimization (STP) algorithm improves optimization capabilities in two ways. It can accelerate optimization convergence, reducing the time needed to find the best solution, and it can navigate complicated solution spaces more effectively to find optical system solutions with smaller (better) error functions compared to traditional damped-least-squares optimization.
Cadence has released a Secure Digital (SD) 4.0 Host Controller Intellectual Property (IP) core, which allows designers to achieve the maximum memory card access performance of up to 312 MByte/s -- 3x the performance of the previous specification. The Cadence SD 4.0 Host Controller IP core is compliant with SD Specification Version 4.0 by the SD Association, with support for Default Speed, High Speed, and Ultra-High Speed Phase I (SDR12, SDR25, SDR50, SDR104, DDR50) as well as Ultra-High Speed Phase II (FD156 and HD312) modes, achieving connection speeds of 1.56 Gbit/s and 3.12 Gbit/s.
Renesas Electronics America, in partnership with IAR Systems, says that developers designing with Renesas's RX or RL78 microcontrollers can get one free license for IAR Embedded Workbench, the popular C/C++ compiler and debugger tool suite. The Renesas/IAR promotion ends March 31, 2014. The promotion is only valid in the Americas. The customer project must use a Renesas RX or RL78 MCU product, and it must be used in a commercial application.
ARM has launched a new accreditation within its ARM Accredited Engineer (AAE) program. The new ARM Accredited MCU Engineer (AAME) accreditation is focused on software aspects of ARMv6 and ARMv7 Cortex-M architecture profiles and is aimed primarily at embedded MCU software engineers who want a broad knowledge of ARM technology. It is biased towards microcontrollers and Cortex-M processors.