A Belgo-Japanese research team has developed an improved process for the integration of germanium-tin films and MOSFETs on silicon substrates. This opens up the possibility of strained GeSn pMOSFETs at sub-10 nm geometries.
The team, drawn from Katholiek University of Leuven, the IMEC research institute at Leuven, and Japan's National Institute of Advanced Industrial Science and Technology (AIST), had developed a solid-phase epitaxy process that overcomes previous limitations in laying down germanium-tin films, such as the limited solubility of tin in germanium (0.5 percent), a tendency to segregation, and a large crystal lattice mismatch.
The interest in germanium-tin is related to the ability to use materials with high electron mobility, such as germanium, and being able to improve that mobility through the use of engineered lattice strain.
The IMEC team has allowed, for the first time they claim, the operation of depletion-mode junctionless GeSn pMOSFET on silicon. The use of a silicon substrate is likely to be have a significant effect on reducing the cost of production, as well as allowing the integration of conventional CMOS and GeSn transistors.
The team has achieved single-crystal films of about 10 nm thickness over silicon that demonstrate tensile strain. This reduces the energy difference between the direct and indirect band transition creating a direct band gap group IV material, IMEC said in a press release. Future research will focus on optimizing the GeSn-on-silicon devices to further increase the channel mobility, IMEC added.
Transmission electron microscope image of NiGeSn metal source and drain MOSFET.
A paper on the development is due to be presented at the Solid State Devices and Materials conference due to be held in Fukuoka, Japan, Sept. 25.