Noticed denser interconnects in the A7, perhaps to accommodate the 2x wider ( 64 bit ) data and address buses within more or less the same real estate. Chipworks could go back and take one more look at their teardown of the Exynos 5 ( 32 bit 8 core ) in the Samsung S4 phone and compare the interconnect w/ the A7 ( both 28 nm by Sam ). Performance can actually take a hit if interconnect conductors & dielectrics are shrunk too much since resistance & capacitance will go up and will become a larger factor as the transistors get faster & more efficient.
It is simply a mystery how Apple and Samsung could be competitors and best of customers. You have Samsung make A7 chip which is there to knock-out Samsung products in the market. A unique case for business schools.
@Tom - How did you determine that the NXP device shown is an LPC18xx device?
The A7 is about 10mm x 10 mm. About 4 of the LPC18A1s fit along one A7 edge. That means the device is about 2.5 mm x 2.5mm. If you look at the ball count, it is 5 x 6 with a 0.35mm pitch which is about 2.5 mm x 2.5 mm. A quick look at the datasheet shows the smallest LPC18xx is 100 balls with about 0.8mm pitch--nearly the same size as the A7. Clearly the device shown on the board is not nearly the same size as the A7--maybe 5% the area!
The math doesn't add up. Are you sure LPC18 and LPC18A1 = LPC18xx?