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Apple M7 From NXP, Says Chipworks

9/20/2013 00:00 AM EDT
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Scott Elder
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Re: impact of 64 bit
Scott Elder   9/21/2013 10:29:33 PM
@Tom - It seems more likely this is a Cortex-M0 given the size.  Still part of the LPC family, but at the low end.

elctrnx_lyf
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Re: impact of 64 bit
elctrnx_lyf   9/22/2013 7:26:27 AM
Does it mean a bad news for ST by losing the accelrometer sensor or is apple still continue with st and skm even with the separate nxp controller

Dick James
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Re: impact of 64 bit
Dick James   9/23/2013 9:59:09 AM
Hi,

We did some poking around on the NXP website, looking at their LPC range of products; and we couldn't find any specific part that matched the look of the LPC18A1, particularly the 30-ball WLCSP packaging. So we've come to the tentative conclusion that this is likely a customised LPC18xx chip built for Apple, similar to those we've seen from Dialog and Cirrus over the years (A1 stands for Apple-1?).

Could be M3, could be M0 (though the latter don't have the LPC18 prefix).

rick merritt
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Re: impact of 64 bit
rick merritt   9/23/2013 11:10:56 AM
This would support Apple's marketing claims that it is a custom chip (sorta).

fmotta
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Re: impact of 64 bit
fmotta   9/23/2013 11:54:36 AM
Chip performance is important and. up to a certain stage multi-core matters.

But, I think that without a reasonable solution for managing the non-parallelizable fraction as described by Gustafson (http://en.wikipedia.org/wiki/Gustafson%27s_law) one cannot get reasonable scaling when the core count exceeds a point (last check it was 4 cores and at 8 one gets diminishing returns for SMP).


So, if SMP is used for more than 4 cores there is a liklihood that we are back to speed fro value. Of course, if there are some dataplane cores that are not within the SMP cluster then they can be removed from the parallizable portion provided they have a reasonable "look-aside" interaction with the other cores.  However, that leaves the challenge of software syncronization.  A challenge that is really best left to hardware by using one of a few known soltions that include hardware managed elastic interface (like queues or free memory pool management).  Or a hardware scheduler can reduce the non-parallelizable portion if well implemented.  I do not believe either of these are available on any existing ARM SoCs yet.  I speculate that the interconnect/cross bar can be saturated on the 8 core design as well.

As a result, I think that the 2-64bit cores can perform well since it can gain from the larger register file.  With the right bit-wize or vector instructions against the 64bit registers then the value increases since more data is registered for one operation.

rick merritt
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Re: impact of 64 bit
rick merritt   9/23/2013 7:22:23 PM
@Dick: Will you be decapping the M7 to find out more about wh9ich core it uses and etc?

rick merritt
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Re: impact of 64 bit
rick merritt   9/23/2013 7:24:15 PM
@fmotta: Thanks for the interesting analysis.

ARM is implying a mix of big and little cores is optimal as you get beyond quad 32-bit. Has anyone heard any thinking about the optimal design points for mobile 64-bit multicore?

goafrit
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Re: More to come
goafrit   10/9/2013 10:27:48 PM
NO RATINGS
That is why most times I think the Apple Samsung rivalry is a media creation. How can you feed your enemy as Apple does with Samung if truly the latter is one?

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