This is a condensed roundup of news and activities associated with EDA and IP over the past week.
Zuken has launched a PCB design productivity app that allows today's generation of PCB designers to interact with layouts using their own tablets or smartphones. The CADSTAR Touch App enables users to control Zuken's CADSTAR expert desktop PCB design software, giving simultaneous control of view and program functions, and enabling faster, more efficient design. The free App is available now with the latest CADSTAR release, which also features enhanced Activ-45 router and pusher technology.
EMA automates 3D STEP models with EDABuilder library automation solution. EDABuilder automates the library process flow. Starting with the data sheet and PDF data sheet extraction, schematic symbols and PCB footprints are created. With the introduction of the 3D STEP modeling and automation of the mechanical models, EDABuilder provides a complete library automation solution.
Real Intent has announced a new release of its Ascent X-Verification System (XV) tool for early functional analysis of digital designs, adding enhancements for initialization analysis, and the detection and management of unknown logic values (X's). All Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional RTL simulation.
Imec and AIST have developed a solid phase epitaxy process to integrate GermaniumTin (GeSn) metal-oxide semiconductor field-effect transistor (MOSFET) devices on silicon. For the first time, operation of depletion-mode junctionless GeSn pMOSFET on silicon was demonstrated, an important step toward achieving tensile strain in MOSFET devices, and increasing their mobility. To improve performance in next-generation scaled CMOS devices, researchers are exploring the integration of novel materials with superior electron mobility. GeSn enables increased switching speed of MOSFET devices and can be used in fast optical communication.
GrammaTech is offering an advanced dynamic analysis tool: Cantata, a unit testing tool for C, C++, and Java. The addition of Cantata will complement CodeSonar, GrammaTech's static analysis tool, providing development teams with advanced software analysis throughout the entire development process. The product is certified to support the IEC 61508 (general industrial), ISO 26262 (automotive), EN 50128 (railways), IEC 60880 (nuclear power), DO-178B/C (avionics), and IEC 62304 (medical devices) standards. The compliance toolkit is free.
The MIPI Alliance has an Analog Reference Interface for Envelope Tracking (eTrak) specification. eTrak is a multisource-vendor, independent interface that provides interoperability between multiple 3G/4G modem chipsets and Envelope Tracking Power Supplies (ETPS), enabling wide deployment of envelope tracking technology. By integrating eTrak into RF modem chipsets and ETPS, the specification allows modem ICs to control the supply voltage of RF power amplifiers, which improves the efficiency of the transmitter, one of the three large power-consuming elements in a mobile device.
Mentor Graphics' solutions have been validated by TSMC with a true 3D stacking test vehicle for TSMC's 3D-IC Reference Flow. The flow expands support from silicon interposer offerings to include TSV-based, stacked die designs. Specific Mentor offerings include capabilities for metal routing and bump implementation, multichip physical verification and connectivity checking, chip interface and TSV parasitics extraction, thermal simulation, and comprehensive pre- and post-package testing.
Similarly, Cadence announced that TSMC has collaborated with Cadence to develop a 3D-IC reference flow that features true 3D stacking. The flow, validated on a memory-on-logic design with a 3D stack based on a Wide I/O interface, enables multiple die integration. It incorporates TSMC 3D stacking technology and Cadence solutions for 3D-IC, including integrated planning tools, a flexible implementation platform, and signoff and electrical/thermal analysis.
Finally, Synopsys has a range of DesignWare Interface IP proven on TSMC's 20 nanometer SoC process. It includes USB, DDR, PCI Express, and MIPI PHY IP. These offer 25 percent lower power consumption or a 30 percent performance improvement, compared to TSMC's 28 nm process.