SAN JOSE, Calif. — Cisco Systems rolled out a new high-end core router and sketched out some specs of the big custom chip driving it. The Cisco nPower X1 is the largest, most integrated chip in the company's ten-year-plus history of designing ASICs. Nevertheless, one analyst called it "a little underwhelming" compared to the competition.
Carriers use core routers in the backbones of their networks. The systems need to support the widest bandwidth, most throughput and greatest port density possible to handle rapidly growing wired and wireless Internet traffic.
The nPower X1 supports 400 Gbit/second aggregate throughput using 336 dual-threaded Tensilica cores and an unspecified number of 10/40/100G Ethernet MACs and hardware accelerators. Unlike 400G chip sets in core routers from Alcatel-Lucent and others, Cisco crammed all the packet processing and traffic management jobs -- including packet buffering, queuing and scheduling -- into a single whopping 598 mm2 die made in a 40nm process.
Cisco believes the silicon integration gives it an edge in packing Terabit/s throughput into a single line card using an undisclosed number of nPower ASICs. The top-end NCS 6000 systems using the chip and shipping today claim 5 Tbits/s throughput per slot and 1.2 Petabit/s at the system level.
The nPower X1 packs 4 billion transistors, roughly half of them for three levels of SRAM cache. It sports hardware accelerators for table look ups, hash functions, quality-of-service and other functions.
Cisco claims the chip pushes external memory to a new level by supporting up to 20 channels of low latency memory, believed to be LLDRAM-III from Renesas and GSI Technology Inc. Cisco would only say the chips are a Gbit-class custom design with low row-cycle times, produced by two memory vendors.
The specialty DRAMs will appear in other Cisco networking systems, but not its x86 servers. The nPower ASIC treats the external DRAM as a single, flat pool of memory.
The company claims nPower is unique in that it can handle 300 million packets/second each with its own feature set. Prior generation routers generally supported fixed feature sets covering all packets.
The nPower chip sports a hardware abstraction layer that lets users program it in high-level languages such as Python and C. It can support emerging software-defined networking protocols, but explicit support for Openflow has not yet been developed for current systems in the field.
"It won't take long to do it, it's just a question of our current priorities," said Nikhil Jayaram, vice president of silicon engineering at Cisco. "We have validated all known Openflow requests -- even those in draft versions -- and we handle them robustly," he said.