The advance program for the 2013 International Electron Devices Meeting (IEDM) has been published. Session 9 on advanced CMOS platforms is likely to be one of the highlights.
In that session, a speaker from Taiwan Semiconductor Manufacturing Co. Ltd. will provide details on the company's 16nm FinFET CMOS process. This will be immediately followed by a paper on the FDSOI process for the 14nm node. The authors of the FinFET paper all come from TSMC, but the authors of the FDSOI paper come from STMicroelectronics, Soitec, Leti, IBM, Globalfoundries, and Renesas.
IEDM, one of the landmark events of the electronic engineering calendar, bridges academic and commercial research in electron-based devices. This year's meeting takes place Dec. 7-9 at the Washington Hilton Hotel.
The foundry TSMC will soon ramp up the production of 20nm circuits and has released 16nm design information. (See: TSMC Releases 16nm FinFET Design Flows.) A TSMC author will present on the 16nm FinFET process that is optimized for mobile and computing applications. According to the abstract of the paper, the process provides twice the logic density and a performance improvement of more than 35 percent (or a 55 percent reduction in power consumpiton) over TSMC's 28nm HKMG planar bulk CMOS process. The following paper on FDSOI -- far from the only FDSOI paper in the conference -- will give details on devices that have a gate length of 20nm but are intended for nodes labeled 14nm.
Intel, which is just beginning to manufacture 14nm FinFET ICs, will be present in the session but with a paper detailing how it can add embedded DRAM to its older 22nm FinFET process (or tri-gate process, as the company calls it). The paper should explain how Intel has achieved more than 100 microseconds of retention time at 95 degrees C for a gigabit array.
Not to be left out, engineers at Fujitsu Semiconductor Ltd. will present Paper 9.6, which addresses the addition of embedded flash nonvolatile memory to its 55nm CMOS logic process that is enhanced using the Deeply Depleted Channel technology licensed from SuVolta Inc. (See: SuVolta Power-Saving Chip Process Enters Production.)
Intel's more advanced process technology at 14nm and below is not scheduled to be discussed in any paper at the conference, but engineers from Intel will present in Session 4 on modeling tunneling field effect transistors (TFETs) in III-V materials for use in a subthreshold voltage manner at nodes of 9nm and below.
Advanced CMOS platforms is just one strand of many that will be represented at IEDM, which will include 215 presentations in 33 sessions. There will be numerous memory papers covering NAND, ReRAM, CBRAM, ferroelectric, and phase-change approaches. The continued expansion of the significance of electronics means that IEDM has an increased emphasis on analog circuits, MEMS sensors, and displays. Circuits and processes for biosensors and bioMEMS will be covered, along with energy harvesting, power devices, magnetics, and spintronics.